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Nanoscale memory cell based on a nanoelectromechanical switched capacitor

Nanoscale memory cell based on a nanoelectromechanical switched capacitor

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Nanoscale memory cell based on a nanoelectromechanical switched capacitor

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  1. Nanoscale memory cell based ona nanoelectromechanical switched capacitor EECS Min Hee Cho

  2. Outline • III Low voltage drive • Low Gate Voltage • Fabrication • SEM image • IV Summary • Summary : Merits • Summary : remaining obstacles • V References/ Q&A I Introduction • Agenda • DRAM & Key idea • Capacitor type • Carbon Nanotube II Mechanical switched capacitor • Fabrication • SEM image • Operation • Switching characteristics J. E. Jang, et al. nature nanotechnology 2008 (Samsung Advanced Institute of Technology & U of Cambridge ) J. E. Jang, et al. APPLIED PHYSICS LETTERS 2008

  3. Outline • III Low voltage drive • Low Gate Voltage • Fabrication • SEM image • IV Summary • Summary : Merits • Summary : remaining obstacles • V References/ Q&A I Introduction • Agenda • DRAM & Key idea • Capacitor structure • Carbon Nanotube II Mechanical switched capacitor • Fabrication • SEM image • Operation • Switching characteristics

  4. Agenda Nanoscale memory cell = DRAM with Carbon nanotube

  5. DRAM & Key idea Schematic drawing of original designs of DRAM patented in 1968. Gate Drain Source Capacitor * Development of DRAM : Cell size is smaller and smaller  TR : On/Off ratio ↓(due to Short channel effect)  Cap : Area of capacitor is also reduced ( Capacitor should be larger to improve performance) * Solution TR : Mechanical switched TR  Cap: Vertical structure ( increase area of capacitor ) or High K

  6. Trench type Capacitor structure Dielectric :small area Cylinder type like “HAT”

  7. Conventional DRAM structure DRAM has several limits as shrinkage * Transistor - low Subthreshold swing (low On/Off ratio) - short channel effect (Off leakage) New challenge for DRAM with CNT * Transistor - Use Electromechanical property not Field effect  On/Off ratio ↑ - Smaller cell area : due to the vertical structure * Additionally, they can use existing silicon technology Gate Capacitor Source Drain New DRAM structure Source Drain Gate Area also reduced

  8. Carbon Nanotube (CNT) They use CNT as electromechanical materials rather than semiconductor material

  9. Outline • III Low voltage drive • Low Gate Voltage • Fabrication • SEM image • IV Summary • Summary : Merits • Summary : remaining obstacles • V References/ Q&A I Introduction • Agenda • DRAM & Key idea • Capacitor type • Carbon Nanotube II Mechanical switched capacitor • Fabrication • SEM image • Operation • Switching characteristics

  10. 0. Make Nb catalyst dot on Substrate I. C2H2 &NH3 gas 600~650oC by PECVD : CNT II. Si3N4 (dielectric & insulator) by PECVD III. Cr by sputtering : upper electrode IV. Si3N4 at Drain removed by wet etching  Si3N4 remaining at bottom of MWCNT strengthen the interface  enhance working reliability Fabrication

  11. SEM image

  12. SEM images CNT diameter : 70nm Gap between CNT : 100nm Length : 3.5um Si3N4 thickness : 40nm For single capacitance: 1.05fF * Total cell: 40,000 ea * MWCNT success rate : 95% * Final cell success rate : 50% (failure due to mainly M/A in litho)

  13. Outline • III Low voltage drive • Low Gate Voltage • Fabrication • SEM image • IV Summary • Summary : Merits • Summary : remaining obstacles • V References/ Q&A I Introduction • Agenda • DRAM & Key idea • Capacitor type • Carbon Nanotube II Mechanical switched capacitor • Fabrication • SEM image • Operation • Switching characteristics

  14. Write Operation Read Write The mutual repulsion between the positive charges on the capacitor and thenanotube in cell 1 prevents the nanotube from making contact with the capacitor, so no current flows, unlike the situation in cell 2, where the nanotube does make contact with the cell. BL of Cell 1 and  apply 0.1V  gate voltage to the 15V  CNT of Cell 1 begins to bend  contacts  charges flow from CNT(BL) to capacitor

  15. Switching characteristics ON Very High gate voltage : Usually DRAM operates at ~1.3V (or less than 2.5V) OFF Threshold gate voltage (Vt) * When gate voltage is higher than Vt, Transistor turns on * Vd increase  Vt decreases due to electrostatic force

  16. Outline • III Low voltage drive • Low Gate Voltage • Fabrication • SEM image • IV Summary • Summary : Merits • Summary : remaining obstacles • V References/ Q&A I Introduction • Agenda • DRAM & Key idea • Capacitor type • Carbon Nanotube II Mechanical switched capacitor • Fabrication • SEM image • Operation • Switching characteristics J. E. Jang, et al. APPLIED PHYSICS LETTERS 2008

  17. Vertical gate structure In this work They make vertical gate and tie it with drain Low Gate Voltage Too high operating voltage (15~20V) ∵ The simple planar gate structure imparts a very small electrostaticforce to the drain  electrostatic force ∝1/d2  Need high voltage APPLIED PHYSICS LETTERS 93, 113105 2008

  18. 4~5 V 14~15V

  19. lift-offprocess (Cr on PMMA removed) PMMA coatingafter the CNT growth process. 30 nm SiNx deposition by PECVD E-beam lithography with substrate tilting 400 nm PMMA coating and ashing process to remove the ThinPMMA on the vertical CNT and gate structure Cr layer deposition Fabrication PolyMethyl MethAcrylate (PMMA): thermoplastic and transparent plastic.

  20. SEM images 1> Operating Gate voltage can be reduced 2> Area also reduced

  21. Outline • III Low voltage drive • Low Gate Voltage • Fabrication • SEM image • IV Summary • Summary : Merits • Summary : remaining obstacles • V References/ Q&A I Introduction • Agenda • DRAM Memory • Basic Operation • Capacitor type • Carbon Nanotube II Mechanical switched capacitor • Fabrication • SEM image • Operation • Switching characteristics

  22. Summary : Merits • Excellent ‘ON–OFF’ ratio – Due to the mechanical switching approach  No ultra-shallow n- or p-type junctions  No thin-gate dielectrics • Compatible with existing silicon technology • Vertical orientation  Cell area ↓ • Placing defined numbers of nanotubes at selected locations

  23. Summary : Remaining Obstacles • High voltage  Vertical gate (14V  4V : still high) • The growth temperature used in this work : 600–650 oC is relatively high for integration with CMOS technology • Still larger (~200nm ) : Need demonstration at smaller size is needed • Randomization of nanotube orientation by thermal fluctuations and gas flows

  24. References • “ Nanoscale memory cell based on a nanoelectromechanical switched capacitor”, J. E. Jang, et al. (Samsung Advanced Institute of Technology & U of Cambridge) Nature 26 Nanotechnology | VOL 3 | JANUARY 2008 • “Nanoelectromechanical switch with low voltage drive” J. E. Jang, et al. APPLIED PHYSICS LETTERS 93, 113105 2008 • Internet search – DRAM / CNT etc.

  25. Q&A Thank you very much See you again!