1 / 22

Defect Tolerance Techniques for Nanoscale Memory Systems

This paper presents an analytical model for a defect-tolerant nanoscale memory system aimed at addressing significant manufacturing defect rates of 10-30% common in this technology. We propose a scheme with low static and dynamic overhead to efficiently identify and avoid defective memory blocks, focusing on 4-KByte page granularity. Our approach combines error-correcting codes with defect mapping and sparing strategies to enhance storage efficiency, lower overhead, and increase yield, paving the way for robust memory solutions in future nanoelectronics.

huyen
Télécharger la présentation

Defect Tolerance Techniques for Nanoscale Memory Systems

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. A Pageable Defect Tolerant Nanoscale Memory System Susmit Biswas, Tzvetan S. Metodi, Frederic T. Chong, Ryan Kastner susmit@cs.ucsb.edu Susmit Biswas

  2. Problem Statement • In a nanoscale memory system with high manufacturing defect rate, we aim to find a scheme with low static and dynamic overhead to identify and avoid the use of defective blocks and make usable memory in the granularity of 4-KByte size pages. Susmit Biswas

  3. Is it a significant problem? • Manufacturing defect • 10 – 30% using Self-assembly • DNA computing • Low yield • Yield decreases with block size Susmit Biswas

  4. Is it a significant problem? Susmit Biswas

  5. Critical Factors • Static Overhead • Bad block information • Dynamic Overhead • Reading and writing latency Susmit Biswas

  6. ECC Overhead source: Likharev07 Susmit Biswas

  7. Contribution • Analytical model • Defect tolerance technique • ECC, defect map, sparing • Study on area benefit • Fixed size block or variable size? Susmit Biswas

  8. Prior Work • Error Correcting Codes [Jeffery04] [Ou04] • Reconfiguration using Defect Map [Tahoori05][Wang06][DeHon05][Likharev-JETC07] • Built-in-self-Repair (BISR) [Bhavsar-ITC99][Schöber-ITC01][Nicolaidis-JET05] • Combination of schemes [Sun06] [Likharev-JETC07][Biswas-ICCAD07] Susmit Biswas

  9. Technique • Benefit from all • Error Correcting Code (BCH) • Strength of code • Defect Map • Level of map • Spare Block • Amount of sparing Susmit Biswas

  10. Technique • Store the defect map in unreliable memory Reconfiguration Map Defect Map Susmit Biswas

  11. Defect Map 101 111 101 Majority Voter 101 Technique • Majority voting to provide correctness Susmit Biswas

  12. System Architecture Data Defect Map Spare Map Metadata Susmit Biswas

  13. Pros and Cons • Pros • Locality of data and metadata • Low static overhead • High yield • Can be pipelined • Support for virtual memory system • Cons • 2s + 1 memory block read • Locality reduces overhead Susmit Biswas

  14. Results: Storage Efficiency Susmit Biswas

  15. Results: Static Overhead Susmit Biswas

  16. Fixed vs. Variable Block Susmit Biswas

  17. Summary • Defect tolerance technique • Combination of static and dynamic scheme • Encoding defect-map with data • Locality of data • Low static overhead • High yield • Higher yield using variable sized page • Static overhead increases Susmit Biswas

  18. Future Work • Efficient BCH module design • Interconnect reliability by redundancy • Cache design using unreliable memory Susmit Biswas

  19. Thanks ! Contact: Susmit Biswas Arch Lab, Department of Computer Science University of California at Santa Barbara susmit@cs.ucsb.edu Online version available at: http://cs.ucsb.edu/~susmit/papers/nanoarch07_nanomemory.pdf Susmit Biswas

  20. References • [Sun06] F. Sun and T. Zhang. “Two Fault Tolerance Design Approaches for Hybrid CMOS/Nanodevice Digital Memories”. Nanoarch 2006 • [Wang06] G. Wang, W. Gong, and R. Kastner. “Defect-Tolerant Nanocomputing Using Bloom Filters”. ICCAD 2006 • [DeHon05] A. DeHon and K. K. Likharev. “Hybrid CMOS /Nanoelectronic Digital Circuits: Devices, Architectures, and Design Automation”. ICCAD '05 • [Tahoori05] M. B. Tahoori. “A Mapping Algorithm for Defect-Tolerance of Recongurable Nano-Architectures”.ICCAD ’05 Susmit Biswas

  21. References • [Likharev07] D. Strukov and K. Likharev, “Defect-Tolerant Architectures for Nanoelectric Crossbar Memories”.Journal of Nanoscience and Nanotechnology, January 2007 • [Jeffery04] C. M. Jeffery, A. Basagalar, and R. J. O. Figueiredo, “Dynamic Sparing and Error Correction Techniques for Fault Tolerance in Nanoscale Memory Structures”.4th IEEE Conference on Nanotechnology 2004. • [Ou04] E. Ou and W. Yang, “Fast Error-Correcting Circuits for Fault-Tolerant Memory”, MTDT, pages 8 - 12, 2004. Susmit Biswas

  22. Reference • [Ramón05] Ramón Compaňó, “Trends in nanoelectronics”, Journal of Nanotechnology 12, 2001 • [Biswas-ICCAD07] Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Frederic T. Chong, Ryan Kastner,“Combining Static and Dynamic Defect-Tolerance Techniques for Nanoscale Memory Systems”, to appear in ICCAD 07 Susmit Biswas

More Related