Advanced Computer Architecture Lecture 18

1. Advanced ComputerArchitectureLecture 18 Write-back cache design Controller University of Portland School of Engineering

2. Project 4 team review • Team Dog University of Portland School of Engineering

3. Project 5 team review • Team Cat • Team Dog University of Portland School of Engineering

4. Cache design example • CPU: B2Logic model • Memory • 256 x 8, RAM (no ROM) • 4X slower then cache, Rdy signal • Cache: direct mapped, write-back • Data: 16 x 8, RAM (no delay) • Tag: 16 x 4 RAM (no delay) University of Portland School of Engineering

5. System schematic University of Portland School of Engineering

6. Driver Main Control System Bus Hit Driver Cache Memory block diagram New bus  University of Portland School of Engineering

7. Possible write-back states • Read-hit • Write-hit • Read-miss-clean • Write-miss-clean • Write back • Read-mis-dirty • Write-miss-dirty NOTE: a write-back causes a dirty-to-clean transition University of Portland School of Engineering

8. Driver Main Control System Bus Hit Driver Cache Write-back, read hit Cache provides data University of Portland School of Engineering

9. Driver Main Control System Bus Hit Driver Cache Write-back, write hit Data written to cache, set mod bit University of Portland School of Engineering

10. Driver Main Control System Bus Hit Driver Cache Write-back, read-miss-clean Main memory provides data Data written to cache, clear mod bit University of Portland School of Engineering

11. Driver Main Control System Bus Hit Driver Cache Write-back, write-miss-clean Data written to cache, set mod bit University of Portland School of Engineering

12. Driver Main Control System Bus Hit Driver Cache Write-back, dirty-to-clean (WB) Upper address comes from cache tag Cache transitions to clean, clear mod bit University of Portland School of Engineering

13. RAM schematic University of Portland School of Engineering

14. 16 x 5 tag R/W# Modrw# Mod Dmod ModDat Dout Match R/W# 4 high Din 4 Hit low A 4 4 16 x 8 cache high Address A 4 8 low Data Din 8 Dout R/W# Crw# Cache memory University of Portland School of Engineering

15. Controller description • Read hit: read cache data and drive it onto bus • Write hit: write data/tag into cache, set Mod • Read miss clean: read data from memory, drive it onto bus, write data/tag into cache, clear Mod • Write miss clean: write data/tag into cache, set Mod • Write back: write cache data into memory, clear Mod, upper address bits from tag memory University of Portland School of Engineering

16. Find controller inputs? • Reset, clk • MemRd, MemWr • Mod • Hit • Ready University of Portland School of Engineering

17. Find controller outputs? • ACK • MBen • Crw# (also goes to tag memory) • Mrw# • Mod data (1-bit), ModRw# • CBen University of Portland School of Engineering

18. WB WB mod? mod? rd mem wr cache rd cache hit? hit? idle State diagram 1 yes yes no no no no yes yes rd wr reset Simple, but too many states and slow University of Portland School of Engineering

19. WB wr cache rd mem rd cache mod? op? wr cache idle State diagram 2 wr rd yes wr rd rd wr hit miss reset Better, but not optimal speed University of Portland School of Engineering

20. Collapsing states • Objective: high speed • Combine states: fewest to solve problem • Read hit • Write hit • Write back • Read miss clean • Write miss clean University of Portland School of Engineering

21. rd miss cl wr miss cl WB wr hit rd hit idle Find transitions? University of Portland School of Engineering

22. Find output table? University of Portland School of Engineering

23. Find actions and states? University of Portland School of Engineering

24. University of Portland School of Engineering

25. 16 x 5 tag R/W# Modrw# Mod Dmod ModDat Dout Match R/W# 4 high Din 4 Hit low A 4 4 16 x 8 cache high Address A 4 8 low Data Din 8 Dout R/W# Crw# Cache memory? University of Portland School of Engineering

26. Find controller inputs? • Reset, clock • Read • Write • Hit • Mod • Rdy University of Portland School of Engineering

27. Find controller outputs? • Mrw#, Mben • Crw#, Cben • Modrw#, ModDat • Ack • Mg1 • WB University of Portland School of Engineering

28. Controller block diagram Cache controller Mg1 Read Mrw# Write Mben Crw# Hit Cben Mod WB Rdy ModDat, Modrw# Ack University of Portland School of Engineering

29. Memory schematic University of Portland School of Engineering

30. rd miss cl wr miss cl WB wr hit rd hit rdy rdy idle Find transitions? (rd+wr)·mod·hit wr·mod·hit S10 S8 S4 S2 S1 rdy wr·hit rdy rd·mod·hit rd·hit S0 reset University of Portland School of Engineering

31. Find output table? University of Portland School of Engineering

32. Find actions and states? University of Portland School of Engineering