1 / 108

Advanced Computer Architecture

Advanced Computer Architecture. Chapter 4 Advanced Pipelining Ioannis Papaefstathiou CS 590.25 Easter 2003 (thanks to Hennesy & Patterson). Chapter Overview. 4.1 Instruction Level Parallelism: Concepts and Challenges 4.2 Overcoming Data Hazards with Dynamic Scheduling

janeeva
Télécharger la présentation

Advanced Computer Architecture

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Advanced Computer Architecture Chapter 4 Advanced Pipelining Ioannis Papaefstathiou CS 590.25 Easter 2003 (thanks to Hennesy & Patterson)

  2. Chapter Overview 4.1 Instruction Level Parallelism: Concepts and Challenges 4.2 Overcoming Data Hazards with Dynamic Scheduling 4.3 Reducing Branch Penalties with Dynamic Hardware Prediction 4.4 Taking Advantage of More ILP with Multiple Issue 4.5 Compiler Support for Exploiting ILP 4.6 Hardware Support for Extracting more Parallelism 4.7 Studies of ILP Chap. 4 - Pipelining II

  3. Chapter Overview Chap. 4 - Pipelining II

  4. Instruction Level Parallelism • ILP is the principle that there are many instructions in code that don’t depend on each other. That means it’s possible to execute those instructions in parallel. • This is easier said than done: • Issues include: • Building compilers to analyze the code, • Building hardware to be even smarter than that code. • This section looks at some of the problems to be solved. 4.1 Instruction Level Parallelism: Concepts and Challenges 4.2 Overcoming Data Hazards with Dynamic Scheduling 4.3 Reducing Branch Penalties with Dynamic Hardware Prediction 4.4 Taking Advantage of More ILP with Multiple Issue 4.5 Compiler Support for Exploiting ILP 4.6 Hardware Support for Extracting more Parallelism 4.7 Studies of ILP Chap. 4 - Pipelining II

  5. Instruction Level Parallelism Pipeline Scheduling and Loop Unrolling Terminology Basic Block - That set of instructions between entry points and between branches. A basic block has only one entry and one exit. Typically this is about 6 instructions long. Loop Level Parallelism - that parallelism that exists within a loop. Such parallelism can cross loop iterations. Loop Unrolling - Either the compiler or the hardware is able to exploit the parallelism inherent in the loop. Chap. 4 - Pipelining II

  6. Instruction Level Parallelism Pipeline Scheduling and Loop Unrolling Simple Loop and its Assembler Equivalent for (i=1; i<=1000; i++) x(i) = x(i) + s; This is a clean and simple example! Loop: LD F0,0(R1) ;F0=vector element ADDD F4,F0,F2 ;add scalar from F2 SD 0(R1),F4 ;store result SUBI R1,R1,8 ;decrement pointer 8bytes (DW) BNEZ R1,Loop ;branch R1!=zero NOP ;delayed branch slot Chap. 4 - Pipelining II

  7. Instruction Level Parallelism Pipeline Scheduling and Loop Unrolling FP Loop Hazards Loop: LD F0,0(R1) ;F0=vector element ADDD F4,F0,F2 ;add scalar in F2 SD 0(R1),F4 ;store result SUBI R1,R1,8 ;decrement pointer 8B (DW) BNEZ R1,Loop ;branch R1!=zero NOP ;delayed branch slot Instruction Instruction Latency inproducing result using result clock cycles FP ALU op Another FP ALU op 3 FP ALU op Store double 2 Load double FP ALU op 1 Load double Store double 0 Integer op Integer op 0 Where are the stalls? Chap. 4 - Pipelining II

  8. Instruction Level Parallelism Pipeline Scheduling and Loop Unrolling FP Loop Showing Stalls 1 Loop: LD F0,0(R1) ;F0=vector element 2 stall 3 ADDD F4,F0,F2 ;add scalar in F2 4 stall 5 stall 6 SD 0(R1),F4 ;store result 7 SUBI R1,R1,8 ;decrement pointer 8Byte (DW) 8 stall 9 BNEZ R1,Loop ;branch R1!=zero 10 stall ;delayed branch slot 10 clocks: Rewrite code to minimize stalls? Instruction Instruction Latency inproducing result using result clock cycles FP ALU op Another FP ALU op 3 FP ALU op Store double 2 Load double FP ALU op 1 Load double Store double 0 Integer op Integer op 0 Chap. 4 - Pipelining II

  9. Instruction Level Parallelism Pipeline Scheduling and Loop Unrolling Scheduled FP Loop Minimizing Stalls 1 Loop: LD F0,0(R1) 2 SUBI R1,R1,8 3 ADDD F4,F0,F2 4 stall 5 BNEZ R1,Loop ;delayed branch 6 SD 8(R1),F4;altered when move past SUBI Now 6 clocks: Now unroll loop 4 times to make faster. Stall is because SD can’t proceed. Swap BNEZ and SD by changing address of SD Instruction Instruction Latency inproducing result using result clock cycles FP ALU op Another FP ALU op 3 FP ALU op Store double 2 Load double FP ALU op 1 Chap. 4 - Pipelining II

  10. Instruction Level Parallelism Pipeline Scheduling and Loop Unrolling Unroll Loop Four Times (straightforward way) 1 Loop: LD F0,0(R1) 2 stall 3 ADDD F4,F0,F2 4 stall 5 stall 6 SD 0(R1),F4 7 LD F6,-8(R1) 8 stall 9 ADDD F8,F6,F2 10 stall 11 stall 12 SD -8(R1),F8 13 LD F10,-16(R1) 14 stall 15 ADDD F12,F10,F2 16 stall 17 stall 18 SD -16(R1),F12 19 LD F14,-24(R1) 20 stall 21 ADDD F16,F14,F2 22 stall 23 stall 24 SD -24(R1),F16 25 SUBI R1,R1,#32 26 BNEZ R1,LOOP 27 stall 28 NOP Rewrite loop to minimize stalls. 15 + 4 x (1+2) +1 = 28 clock cycles, or 7 per iteration Assumes R1 is multiple of 4 Chap. 4 - Pipelining II

  11. Instruction Level Parallelism Pipeline Scheduling and Loop Unrolling Unrolled Loop That Minimizes Stalls 1 Loop: LD F0,0(R1) 2 LD F6,-8(R1) 3 LD F10,-16(R1) 4 LD F14,-24(R1) 5 ADDD F4,F0,F2 6 ADDD F8,F6,F2 7 ADDD F12,F10,F2 8 ADDD F16,F14,F2 9 SD 0(R1),F4 10 SD -8(R1),F8 11 SD -16(R1),F12 12 SUBI R1,R1,#32 13 BNEZ R1,LOOP 14 SD 8(R1),F16 ; 8-32 = -24 14 clock cycles, or 3.5 per iteration What assumptions made when moved code? • OK to move store past SUBI even though changes register • OK to move loads before stores: get right data? • When is it safe for compiler to do such changes? No Stalls!! Chap. 4 - Pipelining II

  12. Instruction Level Parallelism Pipeline Scheduling and Loop Unrolling Summary of Loop Unrolling Example • Determine that it was legal to move the SD after the SUBI and BNEZ, and find the amount to adjust the SD offset. • Determine that unrolling the loop would be useful by finding that the loop iterations were independent, except for the loop maintenance code. • Use different registers to avoid unnecessary constraints that would be forced by using the same registers for different computations. • Eliminate the extra tests and branches and adjust the loop maintenance code. • Determine that the loads and stores in the unrolled loop can be interchanged by observing that the loads and stores from different iterations are independent. This requires analyzing the memory addresses and finding that they do not refer to the same address. • Schedule the code, preserving any dependences needed to yield the same result as the original code. Chap. 4 - Pipelining II

  13. Instruction Level Parallelism Dependencies Compiler Perspectives on Code Movement Compiler concerned about dependencies in program. Not concerned if a HW hazard depends on a given pipeline. • Tries to schedule code to avoid hazards. • Looks for Data dependencies (RAW if a hazard for HW) • Instruction i produces a result used by instruction j, or • Instruction j is data dependent on instruction k, and instruction k is data dependent on instruction i. • If dependent, can’t execute in parallel • Easy to determine for registers (fixed names) • Hard for memory: • Does 100(R4) = 20(R6)? • From different loop iterations, does 20(R6) = 20(R6)? Chap. 4 - Pipelining II

  14. Instruction Level Parallelism Data Dependencies Compiler Perspectives on Code Movement Where are the data dependencies? 1 Loop: LD F0,0(R1) 2 ADDD F4,F0,F2 3 SUBI R1,R1,8 4 BNEZ R1,Loop ;delayed branch 5 SD 8(R1),F4 ;altered when move past SUBI Chap. 4 - Pipelining II

  15. Instruction Level Parallelism Name Dependencies Compiler Perspectives on Code Movement • Another kind of dependence called name dependence: two instructions use same name (register or memory location) but don’t exchange data • Anti-dependence (WAR if a hazard for HW) • Instruction j writes a register or memory location that instruction i reads from and instruction i is executed first • Output dependence (WAW if a hazard for HW) • Instruction i and instruction j write the same register or memory location; ordering between instructions must be preserved. Chap. 4 - Pipelining II

  16. Instruction Level Parallelism Name Dependencies Compiler Perspectives on Code Movement 1 Loop: LD F0,0(R1) 2 ADDD F4,F0,F2 3 SD 0(R1),F4 4 LD F0,-8(R1) 5 ADDD F4,F0,F2 6 SD -8(R1),F4 7 LD F0,-16(R1) 8 ADDD F4,F0,F2 9 SD -16(R1),F4 10 LD F0,-24(R1) 11 ADDD F4,F0,F2 12 SD -24(R1),F4 13 SUBI R1,R1,#32 14 BNEZ R1,LOOP 15 NOP How can we remove these dependencies? Where are the name dependencies? No data is passed in F0, but can’t reuse F0 in cycle 4. Chap. 4 - Pipelining II

  17. Instruction Level Parallelism Name Dependencies Compiler Perspectives on Code Movement • Again Name Dependencies are Hard for Memory Accesses • Does 100(R4) = 20(R6)? • From different loop iterations, does 20(R6) = 20(R6)? • Our example required compiler to know that if R1 doesn’t change then:0(R1) ≠ -8(R1) ≠ -16(R1) ≠ -24(R1) There were no dependencies between some loads and stores so they could be moved around each other Chap. 4 - Pipelining II

  18. Instruction Level Parallelism Control Dependencies Compiler Perspectives on Code Movement • Final kind of dependence called control dependence • Example if p1 {S1;}; if p2 {S2;}; S1 is control dependent on p1 and S2 is control dependent on p2 but not on p1. Chap. 4 - Pipelining II

  19. Instruction Level Parallelism Control Dependencies Compiler Perspectives on Code Movement • Two (obvious) constraints on control dependences: • An instruction that is control dependenton a branch cannot be moved before the branch so that its execution is no longer controlled by the branch. • An instruction that is not control dependenton a branch cannot be moved to after the branch so that its execution is controlled by the branch. • Control dependencies relaxed to get parallelism; get same effect if preserve order of exceptions (address in register checked by branch before use) and data flow (value in register depends on branch) Chap. 4 - Pipelining II

  20. Instruction Level Parallelism Control Dependencies Where are the control dependencies? Compiler Perspectives on Code Movement 1 Loop: LD F0,0(R1) 2 ADDD F4,F0,F2 3 SD 0(R1),F4 4 SUBI R1,R1,8 5 BEQZ R1,exit 6 LD F0,0(R1) 7 ADDD F4,F0,F2 8 SD 0(R1),F4 9 SUBI R1,R1,8 10 BEQZ R1,exit 11 LD F0,0(R1) 12 ADDD F4,F0,F2 13 SD 0(R1),F4 14 SUBI R1,R1,8 15 BEQZ R1,exit .... Chap. 4 - Pipelining II

  21. Instruction Level Parallelism Loop Level Parallelism When Safe to Unroll Loop? • Example: Where are data dependencies? (A,B,C distinct & non-overlapping) 1. S2 uses the value, A[i+1], computed by S1 in the same iteration. 2. S1 uses a value computed by S1 in an earlier iteration, since iteration i computes A[i+1] which is read in iteration i+1. The same is true of S2 for B[i] and B[i+1]. This is a “loop-carried dependence” between iterations • Implies that iterations are dependent, and can’t be executed in parallel • Note the case for our prior example; each iteration was distinct for (i=1; i<=100; i=i+1) { A[i+1] = A[i] + C[i]; /* S1 */ B[i+1] = B[i] + A[i+1]; /* S2 */} Chap. 4 - Pipelining II

  22. Instruction Level Parallelism Loop Level Parallelism When Safe to Unroll Loop? • Example: Where are data dependencies? (A,B,C,D distinct & non-overlapping) 1. No dependence from S1 to S2. If there were, then there would be a cycle in the dependencies and the loop would not be parallel. Since this other dependence is absent, interchanging the two statements will not affect the execution of S2. 2. On the first iteration of the loop, statement S1 depends on the value of B[1] computed prior to initiating the loop. for (i=1; i<=100; i=i+1) { A[i+1] = A[i] + B[i]; /* S1 */ B[i+1] = C[i] + D[i]; /* S2 */} Chap. 4 - Pipelining II

  23. Instruction Level Parallelism Loop Level Parallelism Now Safe to Unroll Loop? (p. 240) A[1] = A[1] + B[1]; for (i=1; i<=99; i=i+1) { B[i+1] = C[i] + D[i]; A[i+1] = + A[i+1] + B[i+1];} B[101] = C[100] + D[100]; for (i=1; i<=100; i=i+1) { A[i+1] = A[i] + B[i]; /* S1 */ B[i+1] = C[i] + D[i];} /* S2 */ No circular dependencies. OLD: Loop caused dependence on B. Have eliminated loop dependence. NEW: Chap. 4 - Pipelining II

  24. Dynamic Scheduling • Dynamic Scheduling is when the hardware rearranges the order of instruction execution to reduce stalls. • Advantages: • Dependencies unknown at compile time can be handled by the hardware. • Code compiled for one type of pipeline can be efficiently run on another. • Disadvantages: • Hardware much more complex. 4.1 Instruction Level Parallelism: Concepts and Challenges 4.2 Overcoming Data Hazards with Dynamic Scheduling 4.3 Reducing Branch Penalties with Dynamic Hardware Prediction 4.4 Taking Advantage of More ILP with Multiple Issue 4.5 Compiler Support for Exploiting ILP 4.6 Hardware Support for Extracting more Parallelism 4.7 Studies of ILP Chap. 4 - Pipelining II

  25. The idea: Dynamic Scheduling HW Schemes: Instruction Parallelism • Why in HW at run time? • Works when can’t know real dependence at compile time • Compiler simpler • Code for one machine runs well on another • Key Idea: Allow instructions behind stall to proceed. • Key Idea: Instructions executing in parallel. There are multiple execution units, so use them. DIVD F0,F2,F4 ADDD F10,F0,F8 SUBD F12,F8,F14 • Enables out-of-order execution => out-of-order completion Chap. 4 - Pipelining II

  26. The idea: Dynamic Scheduling HW Schemes: Instruction Parallelism • Out-of-order execution divides ID stage: 1. Issue—decode instructions, check for structural hazards 2. Read operands—wait until no data hazards, then read operands • Scoreboards allow instruction to execute whenever 1 & 2 hold, not waiting for prior instructions. • A scoreboard is a “data structure” that provides the information necessary for all pieces of the processor to work together. • We will use In order issue, out of order execution, out of order commit ( also called completion) • First used in CDC6600. Our example modified here for DLX. • CDC had 4 FP units, 5 memory reference units, 7 integer units. • DLX has 2 FP multiply, 1 FP adder, 1 FP divider, 1 integer. Chap. 4 - Pipelining II

  27. Dynamic Scheduling Using A Scoreboard Scoreboard Implications • Out-of-order completion => WAR, WAW hazards? • Solutions for WAR • Queue both the operation and copies of its operands • Read registers only during Read Operands stage • For WAW, must detect hazard: stall until other completes • Need to have multiple instructions in execution phase => multiple execution units or pipelined execution units • Scoreboard keeps track of dependencies, state or operations • Scoreboard replaces ID, EX, WB with 4 stages Chap. 4 - Pipelining II

  28. Dynamic Scheduling Using A Scoreboard Four Stages of Scoreboard Control 1. Issue —decode instructions & check for structural hazards (ID1) If a functional unit for the instruction is free and no other active instruction has the same destination register (WAW), the scoreboard issues the instruction to the functional unit and updates its internal data structure. If a structural or WAW hazard exists, then the instruction issue stalls, and no further instructions will issue until these hazards are cleared. Chap. 4 - Pipelining II

  29. Dynamic Scheduling Using A Scoreboard Four Stages of Scoreboard Control 2. Read operands —wait until no data hazards, then read operands (ID2) A source operand is available if no earlier issued active instruction is going to write it, or if the register containing the operand is being written by a currently active functional unit. When the source operands are available, the scoreboard tells the functional unit to proceed to read the operands from the registers and begin execution. The scoreboard resolves RAW hazards dynamically in this step, and instructions may be sent into execution out of order. Chap. 4 - Pipelining II

  30. Dynamic Scheduling Using A Scoreboard Four Stages of Scoreboard Control 3. Execution—operate on operands (EX) The functional unit begins execution upon receiving operands. When the result is ready, it notifies the scoreboard that it has completed execution. 4. Write result—finish execution (WB) Once the scoreboard is aware that the functional unit has completed execution, the scoreboard checks for WAR hazards. If none, it writes results. If WAR, then it stalls the instruction. Example: DIVD F0,F2,F4 ADDD F10,F0,F8 SUBD F8,F8,F14 Scoreboard would stall SUBD until ADDD reads operands Chap. 4 - Pipelining II

  31. Dynamic Scheduling Using A Scoreboard Three Parts of the Scoreboard 1. Instruction status—which of 4 steps the instruction is in 2. Functional unit status—Indicates the state of the functional unit (FU). 9 fields for each functional unit Busy—Indicates whether the unit is busy or not Op—Operation to perform in the unit (e.g., + or –) Fi—Destination register Fj, Fk—Source-register numbers Qj, Qk—Functional units producing source registers Fj, Fk Rj, Rk—Flags indicating when Fj, Fk are ready 3. Register result status—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions will write that register Chap. 4 - Pipelining II

  32. Instruction status Issue Read operands Execution complete Write result Dynamic Scheduling Using A Scoreboard Detailed Scoreboard Pipeline Control Bookkeeping Wait until Busy(FU) yes; Op(FU) op; Fi(FU) `D’; Fj(FU) `S1’; Fk(FU) `S2’; Qj Result(‘S1’); Qk Result(`S2’); Rj not Qj; Rk not Qk; Result(‘D’) FU; Not busy (FU) and not result(D) Rj No; Rk No Rj and Rk Functional unit done f(if Qj(f)=FU then Rj(f) Yes);f(if Qk(f)=FU then Rj(f) Yes); Result(Fi(FU)) 0; Busy(FU) No f((Fj( f )≠Fi(FU) or Rj( f )=No) & (Fk( f ) ≠Fi(FU) or Rk( f )=No)) Chap. 4 - Pipelining II

  33. Dynamic Scheduling Using A Scoreboard Scoreboard Example This is the sample code we’ll be working with in the example: LD F6, 34(R2) LD F2, 45(R3) MULT F0, F2, F4 SUBD F8, F6, F2 DIVD F10, F0, F6 ADDD F6, F8, F2 What are the hazards in this code? Latencies (clock cycles): LD 1 MULT 10 SUBD 2 DIVD 40 ADDD 2 Chap. 4 - Pipelining II

  34. Dynamic Scheduling Using A Scoreboard Scoreboard Example Chap. 4 - Pipelining II

  35. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 1 Issue LD #1 Shows in which cycle the operation occurred. Chap. 4 - Pipelining II

  36. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 2 LD #2 can’t issue since integer unit is busy. MULT can’t issue because we require in-order issue. Chap. 4 - Pipelining II

  37. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 3 Chap. 4 - Pipelining II

  38. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 4 Chap. 4 - Pipelining II

  39. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 5 Issue LD #2 since integer unit is now free. Chap. 4 - Pipelining II

  40. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 6 Issue MULT. Chap. 4 - Pipelining II

  41. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 7 MULT can’t read its operands (F2) because LD #2 hasn’t finished. Chap. 4 - Pipelining II

  42. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 8a DIVD issues. MULT and SUBD both waiting for F2. Chap. 4 - Pipelining II

  43. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 8b LD #2 writes F2. Chap. 4 - Pipelining II

  44. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 9 Now MULT and SUBD can both read F2. How can both instructions do this at the same time?? Chap. 4 - Pipelining II

  45. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 11 ADDD can’t start because add unit is busy. Chap. 4 - Pipelining II

  46. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 12 SUBD finishes. DIVD waiting for F0. Chap. 4 - Pipelining II

  47. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 13 ADDD issues. Chap. 4 - Pipelining II

  48. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 14 Chap. 4 - Pipelining II

  49. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 15 Chap. 4 - Pipelining II

  50. Dynamic Scheduling Using A Scoreboard Scoreboard Example Cycle 16 Chap. 4 - Pipelining II

More Related