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Strategies for High Luminosity at D Ø (the next trigger upgrades)

Strategies for High Luminosity at D Ø (the next trigger upgrades). D Ø Physics and Triggering Big Plans and Their Consequences The D Ø Trigger Upgrade L1Cal: Algorithms and Challenges Where Does it All Fit In ?. Hal Evans Columbia University. D Ø à la carte. some Run II Physics Goals.

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Strategies for High Luminosity at D Ø (the next trigger upgrades)

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  1. Strategies for High Luminosity at DØ(the next trigger upgrades) DØ Physics and Triggering Big Plans and Their Consequences The DØ Trigger Upgrade L1Cal: Algorithms and Challenges Where Does it All Fit In ? Hal Evans Columbia University Alberta Seminar: 6-Feb-04

  2. DØ à la carte Alberta Seminar: 6-Feb-04

  3. some Run II Physics Goals Alberta Seminar: 6-Feb-04

  4. Swimming in Data Conclusion:too much Physics ! Alberta Seminar: 6-Feb-04

  5. jet jet jet jet jet Event Topologies Background: QCD Alberta Seminar: 6-Feb-04

  6. Wheat from Chaff Alberta Seminar: 6-Feb-04

  7. 2.5 MHz L14.2 s(128 terms) F’work 3 kHz L2100 s(128 terms) 1 kHz Data L350 ms(48 nodes) 50 Hz Trigger Happy Level-1: (2.5 MHz  3 kHz) • Single Sub-Det’s • Towers, Tracks, ET-miss • Some correlationss • Not deadtimeless Level-2: (3 kHz  1 kHz) • Correlations • Calibrated Data • Phys Objs: e,,j,,ET-miss Level-3: (1 kHz  50 Hz) • Simple Reco • Physics Algo’s Alberta Seminar: 6-Feb-04

  8. Detector Level 1 Level 2 2.5 Mhz 3 khz 1 khz CAL L1Cal L2Cal c/f PS L1PS L2PS CFT L1CTT L2CTT SMT L2STT L1Mu MU L2Mu FPD L1FPD Global L2 Lumi Framework Level 3 DØ L1 & L2 Triggers: Run IIa Alberta Seminar: 6-Feb-04

  9. DØ Data So Far • emittance at injection • chromaticity • alignment / helices • reliability: Pfail(1hr) ~2% • 17 hr stores  1/3 end in comp failure 234 pb-1 recorded (Run I: 125 pb-1) Current Issues Alberta Seminar: 6-Feb-04

  10. dedicated hep 30 tev helix 25 stacktail upgrade 20 recycler & e-cool Peak Luminosity (x1031cm-2sec-1) 15 slip stacking 10 5 we are here 0 10/02 10/03 10/04 10/05 10/06 10/07 10/08 10/09 Accelerator Plan: July 2003 2.81032 7.7 5.5 1.61032 <Interactions> per bunch x’ing 1.3 Alberta Seminar: 6-Feb-04

  11. Every Silver Lining has Its Cloud • Event Rates • L1 bandwidth limit • Fake Rates (occup.) • interactions per crossing • Jet Turn-On (L1/Tot) • Trig = 1 TT > 5 GeV • || < 0.9 • Fake Track Rate • Trig = 1 Trk (Pt > 10 GeV) Alberta Seminar: 6-Feb-04

  12. Bare-Bones Triggers: Run IIa Luminosity21032 BC396 ns L1 Limit~3 kHz Alberta Seminar: 6-Feb-04

  13. Can You Believe Us? • Background Rate Simulation • PYTHIA QCD Monte Carlo • + Poisson Distrib. of PYTHIA min-bias events • Agreement is pretty good ! Jet & EM Trigger Ratesdata vs sim qcd bgrd CFT Occupancy vs Layerdata vs sim min-bias Alberta Seminar: 6-Feb-04

  14. Growing Pains for the Trigger Note: will concentrate mainly on L1 in this talk Alberta Seminar: 6-Feb-04

  15. History Lessons Original Run IIb Plan • Accel: >15 fb-1, BC=132ns • Exp’s: Si, Trigger, DAQ • Higgs Reach  180 GeV • Extensive Reviews Reality Strikes • accelerator plan driven by physics goals rather than machine realities Causing Consequences • Si upgrades cancelled (foolishly) • driven by Integ. Lumi • DØ adding inner Si layer • recovers some of orig. upgrade gain Trigger upgrades unchanged • driven by Inst. Lumi Run II Higgs Working Group Alberta Seminar: 6-Feb-04

  16. Trigger Upgrade Overview Main Changes at Level-1 • L1Cal completely new • L1CTT trk-finding DBs • Cal-Trk copy from L1Mu Level-2 • STT changed SMT • Gen add processing General Plan • fewest possible changes • small perturb on DØ physics commissioning Detector Level 1 Level 2 2.5 Mhz 3 khz 1 khz CAL L1Cal L2Cal CalTrk c/f PS L1PS L2PS CFT L1CTT L2CTT SMT L2STT L1Mu MU L2Mu FPD L1FPD Global L2 Lumi Framework Level 3 Alberta Seminar: 6-Feb-04

  17. Run IIbsinglets define roads Run IIadoublets define roads L1 Track Trigger Algorithm 80 – 4.5o Sectors Alberta Seminar: 6-Feb-04

  18. L1Cal Quadrant(8 cluster posn’s) L1CTT Track(20 / quadrant) Matching Tracks & Cal at Level-1 Big Benefits from Matching Tracking & Cal. Information • geometrical match • energy match Current System • Track (80)  Cal Quadr (4) • (not yet implemented) New System • Track (80)  Cal Clust (32) • Factor 2-3 rate reduction • Preliminary Studies • eff.(H) ~ 30% • Rate ~ 125 Hz Design based on L1Muon • limits risk Alberta Seminar: 6-Feb-04

  19. DØ U-LAr Calorimeter Hermetic • || < 4.2 Good E-Res • EM: ~14%/E  <1% • Jet: ~80%/E Granular Readout • =0.10.1 • 4 EM samples • 4-5 Had Trigger Elements • 32  x 40 x(EM & EM+H) 2560 TTs • ICR not used InterCryostat Detector (ICD) Massless Gaps(no absorb) Coarse Hadr. Fine Hadr. Electro-Mag. Alberta Seminar: 6-Feb-04

  20. Cal Preamp PrecisionReadout Trigger Pickoff BLS Cardon detector Analog TT Sums CTFE4 EM + 4 H TT EEt EM & EM+H Compare & Sums ADC Sum / Add Trees L1 Cal in Run IIa L1Cal in Run IIa • Using Run Ib System (1990) • Unit = Trigger Tower (TT) •  = 0.20.2  4032  1280 EM + 1280 Had • Compromise b/w Jet & EM • EM Molière Radius ~0.02 • Jet Radius ~0.5 Trigger Outputs • # EM TTs > 4 Thr • H Et veto avail. – not used • also avail. by quadrant • # EM+H TTs > 4 Thr • also avail. by quadrant • Global ET Sum • Missing ET (Ex & Ey) Alberta Seminar: 6-Feb-04

  21. L1Cal is Key L1 Calorimeter Trigger is the primary mechanism for collecting: e/, Jets, Invisible Particles (MET) Alberta Seminar: 6-Feb-04

  22. Signal rise > 132 ns cross thrsh before peak trigger on wrong x’ing affects high-Et events prevents 132 ns running Poor Et-res. (Jet,EM,MEt) slow turn-on curves 5 Gev TT thresh  80% eff. for 40 GeV jets low thresholds  unacceptable rates at L = 21032 396 ns EM TT Signal 132 ns Run IIa Limitations Alberta Seminar: 6-Feb-04

  23. ADF Processing Chain ADC 2 8 Tap FIR 3 Point Peak Detector 2 ET Look Up Table Analog input Serializer BC rate: 7.57 MHz 10 bit 30.28 MHz 10 bit 15.14 MHz 11 bit 15.14 MHz 11 bit 7.57 MHz 8 bit 7.57 MHz Run IIb Solutions (1) • Solution to Signal Rise Time: Digital Filtering • digitize Cal trigger signals • 8-tap FIR (6-bit coeff’s) + Peak Detector run at BC2 • reformats output for transmission to physics algo stage • Benefits • allows running at 132 ns (keeps this option open) • improvements in energy resolution (under study) • note: this stage is necessary as input to algo stage Alberta Seminar: 6-Feb-04

  24. Run IIb Solutions (2) • Solution for Rates: Sliding Windows Algorithm • Et cluster local max. search on 4032 () TT grid • Jet, EM & Tau algo’s • Better calc of missing Et • Topological Triggers • Jet, EM clust output for matching with L1 Tracks • Benefits • 2.5–3 Jet Rate reduction at const. eff. • ZHvvbb Rate: 2.10.8 kHz • Similar gains for EM &Tau • MEt, Topological Triggers under study Jet Algo EM Algo Tau Algo Alberta Seminar: 6-Feb-04

  25. Turn-on Curvesfrom data x3 ZH  bb Algorithm Results Et(trig) / Et(reco)w/ Run IIa Data! More Possibilties • improved EM turn-on • new tau triggers • topological triggers • improved Met resolution TTsAve = 0.4RMS/Ave = 0.5 Sliding WindowsAve = 0.8RMS/Ave = 0.2 Alberta Seminar: 6-Feb-04

  26. What We Get ! Luminosity21032 BC396 ns L1 Limit~3 kHz Alberta Seminar: 6-Feb-04

  27. The Run IIb L1Cal System Collaborators • Columbia/Nevis • Fermilab • Northeastern • Michigan State • Saclay • U. Illinois, Chicago Alberta Seminar: 6-Feb-04

  28. Design Constraints System Design driven by Data Sharing requirments of Sliding Windows Algorithm • 1 Local Max search requires data from 66 TTs • Minimize Data Duplication  30 ADFs (960 TTs)  1 TAB Data Transmitted Serially using LVDS • 3 identical copies per ADF • LVDS transmission at 424 MHz  >0.1 Tbit/s in System • Use National Channel Link Chipset (48:8 mux) • Compact Cables: AMP with 2mm HM connectors Serial Arithmetic on TAB • pins on FPGAs Serial Adder Alberta Seminar: 6-Feb-04

  29. ADF Prototype ~1300 components on both sides of a 14-layer class 6 PCB Logic FPGAs DC/DC Conv. Analog & ADCs VME Interface Channel Link Xmit VME to TABs(3 cables) BLS Input(32 TTs) Alberta Seminar: 6-Feb-04

  30. TAB Prototype Channel LinkReceivers (x30) DC/DC conv power VME/SCL L2/L3 Output (optical) ADF Inputs (x30) Output to GAB Global Chip Output to Cal-Track (x3) Sliding WindowsChips (x10) Alberta Seminar: 6-Feb-04

  31. The Short and Winding Road Total Price Tag: $1.4M Alberta Seminar: 6-Feb-04

  32. Need to assure that downtime due to installation is minimized Access to Real TT Data using “Splitter” Boards no perturbation of Run IIa L1Cal signals Test System set up near Detector first look at real performance noise, digital filter algo, trigger terms… experience running the boards interaction w/ trig. framework Critical to have a Well Understood system before Final Installation Getting Our Hands on Data Alberta Seminar: 6-Feb-04

  33. Looking to the Future DØ L1Cal as LHC Testbed • Atlas uses sliding windows • experience w/ digital filter • important differences • BCid, saturation… Atlas L1Calo Alberta Seminar: 6-Feb-04

  34. Conclusions • Tevatron Luminosity is Steadily Increasing • goal is 4–9 fb-1 by start of LHC physics • DØ Physics Goals are Ambitious • wide range of physics topics • new phenom/higgs, top, W/Z, b-physics, qcd • Inst. Lumi Gains  Upgrade of Trigger • retain sensitivity to high Pt processes • main hardware component at Level-1 • State of the Art Electronics / Novel Algorithms • a test bed for even more sophisticated systems at the LHC Alberta Seminar: 6-Feb-04

  35. Backup Slides Alberta Seminar: 6-Feb-04

  36. Physics Goals References • Run II Tevatron Working Groups • http://www-theory.fnal.gov • Publications • Higgs hep-ph/0010338 • SUGRA hep-ph/0003154 • BTMSSM hep-ph/0006162 • RPV hep-ph/9906224 • GM SUSY hep-ph/0008070 • Electroweak Fermilab-PUB-00/297 • Top see web (above) • B hep-ph/0201071 Alberta Seminar: 6-Feb-04

  37. VME/SCL Board • New Comp. of TAB/GAB system • proposed: Feb 03 • change control: Mar 03 • Interfaces to • VME (custom protocol) • not enough space on TAB for standard VME • D0 Trigger Timing (SCL) • (previously part of GAB) • Why Split off from GAB • simplifies system design & maintenance • allows speedy testing of prototype TAB • Fully Tested: Jun 12 local osc’s & f’out (standalone runs) VME interface SCL interface serial out x9(VME & SCL) Fully Tested Alberta Seminar: 6-Feb-04

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