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Aeroflex RadHard FPGA ESD Test Results January 2005

Aeroflex RadHard FPGA ESD Test Results January 2005. Gerald Matia Manager, Analytical Services Aeroflex Colorado Springs (719) 594-8137 Matia at aeroflex dot com. Outline. ESD Testing Results / Classification Failure Analysis Conclusion. ESD Testing. Test Methods

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Aeroflex RadHard FPGA ESD Test Results January 2005

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  1. Aeroflex RadHard FPGA ESD Test Results January 2005 Gerald Matia Manager, Analytical Services Aeroflex Colorado Springs (719) 594-8137 Matia at aeroflex dot com

  2. Outline • ESD Testing • Results / Classification • Failure Analysis • Conclusion

  3. ESD Testing • Test Methods • HBM: Mil-Std-883, TM3015 • CDM: JESD22-C101C • MM: JESD22-A115-A • Unprogrammed and Programmed devices tested • ViaLinks (antifuses) are isolated from the ESD protection structures by several stages of circuitry • At Failing Voltages, in all cases damage resulted in I/O pin or VCCIO power shorts to ground • No damage observed in adjacent passing buffers

  4. ESD Testing

  5. ESD Stress Results • Specification • HBM: Class 1 = 0-1,999V, Class 2 = 2,000 – 3,999V, Class 3 = 4000+ V • CDM: Class 1 = <200V, Class 2 = 200 to <500V, Class 3 = 500-1000V, Class 4 = >1000V • MM: Class A = 200V or less, Class B 200V - 400V, Class C = 400+ V • Buffer Configurations Tested • LVCMOS • LVTTL • PCI

  6. Ground DP18 Passed DP15 failed Not tested Not tested

  7. Conclusion • ESD Tolerance Results are good • ESD Protection circuitry layout performs well • No change in pre-stress to post-stress electrical test results indicating no damage to device below failing voltage levels

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