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Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC

Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC. Wei Jiang and Vishwani D. Agrawal Electrical and Computer Engineering Auburn University 17th IEEE North Atlantic Test Workshop. Outline. Overview Test of DAC Polynomial fitting algorithm

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Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC

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  1. Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC Wei Jiang and Vishwani D. Agrawal Electrical and Computer Engineering Auburn University 17th IEEE North Atlantic Test Workshop

  2. Outline • Overview • Test of DAC • Polynomial fitting algorithm • DAC calibration by dithering DAC • Test and calibration of ADC • Simulation results • Summary The 17th IEEE North Atlantic Test Workshop’08

  3. Overview • Built-in test solution for mixed-signal system-on-chips (SoCs) • Testing and characterizing non-linearity of on-chip DAC/ADCs • Output calibration and error compensation for better linearity • Low cost for design and manufacturing The 17th IEEE North Atlantic Test Workshop’08

  4. Typical Mixed-signal SoC The 17th IEEE North Atlantic Test Workshop’08

  5. Non-linearity Errors INL error INL error The 17th IEEE North Atlantic Test Workshop’08

  6. Proposed BIST Scheme Lineardigital code outputs Linearanalog outputs The 17th IEEE North Atlantic Test Workshop’08

  7. Third-Order Polynomial Fitting • Proposed by S.K. Sunter in ITC’96 • Divide DAC transfer function into four sections • Combine function outputs of each section (S0, S1, S2, S3) • Calculate four coefficients (b0, b1, b2, b3) by easily-generated equations The 17th IEEE North Atlantic Test Workshop’08

  8. Test of On-Chip DAC Fitting for INL error The 17th IEEE North Atlantic Test Workshop’08

  9. Design of ΣΔ Modulator 3 LSB 104.10dB The 17th IEEE North Atlantic Test Workshop’08

  10. Simulation Results for On-Chip DAC On-chip DAC INL error Polynomial fitting for INL error Fitting results through 6-bit dithering DAC Final analog outputs by calibrated DAC The 17th IEEE North Atlantic Test Workshop’08

  11. Test of On-Chip ADC INL error Calibrated DAC to generate linear analog output The 17th IEEE North Atlantic Test Workshop’08

  12. Summary • A built-in test and calibration scheme for on-chip DAC/ADC is proposed • A polynomial fitting algorithm is used to fix non-linearity error of DAC/ADC outputs • Fault tolerance factor can be chosen for different applications • Simulation results show that linearity is significantly improved after calibration • Future research work: • Reduce the testing time • Improve the fitting algorithm for even higher linearity The 17th IEEE North Atlantic Test Workshop’08

  13. THANKS Q&A

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