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ECE 412: Microcomputer Laboratory

ECE 412: Microcomputer Laboratory. Lecture 12: VGA Video. Objectives. Describe the output format of the ADV7183B video decoder Introduce the VGA video “standard” Provide an outline of how to use the triple DAC chip on the XUP board to drive video output. Review Questions.

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ECE 412: Microcomputer Laboratory

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  1. ECE 412: Microcomputer Laboratory Lecture 12: VGA Video Lecture 12

  2. Objectives • Describe the output format of the ADV7183B video decoder • Introduce the VGA video “standard” • Provide an outline of how to use the triple DAC chip on the XUP board to drive video output Lecture 12

  3. Review Questions • Describe the clock negotiation protocol of I2C using a timing diagram. • Explain how the negotiation protocol helps to make the bus serve both high-end and low-end device environments. Lecture 12

  4. wait state count high period CLK1 CLK2 SCL Review Questions 1 When the master asserts control over the bus, it does so by pulling the SCL line low. When other devices detect this, they too pull the SCL line low. Since the SCL line is normally pulled up by a resistor, the line will remain low until released by all devices. Each device releases the SCL line at a speed at which it is able to operate; thus the fastest devices release the line first, the slowest last. When the SCL line finally returns high, the controlling device knows that the slowest device has released, and therefore knows that the time it took from the beginning until the current point is the rate at which the slowest device can operate. When all devices see clock go high, begin counting off (wait for) its clock high period and pull the SCL line low. SCL goes low when the first device reaches the end of its clock high period – SCL high period is determined by the shortest clock HIGH period. Lecture 12

  5. Review Questions 2 I2C bus is an asynchronous bus and can adapt to both slow and fast devices. The bus operates at a speed so that all members of the bus can successfully be used. By allowing for interoperation of both fast and slow members, high- and low-end devices can function within the same environment. Lecture 12

  6. ADV7183B Output Format • Note Timing Reference Code that signals start/end of line • Do not try to count clock cycles to determine start/end of line, use reference code as per CCIR656 standard (posted app note) • Ok to count lines • You’ll probably need to downsample to get an image you can display • See p.39 of ADV7183B datasheet Lecture 12

  7. YUV Format • Image encoded as Y (brightness) and U, V (color) components • U represents the color difference between blue and yellow, and V represents the color difference between red and cyan. • Take advantage of fact that human eye is more sensitive to changes in brightness than color to reduce size of images • Encode brightness information for each pixel, share color information between adjacent pixels • Called “4:2:2” format, although our video decoder outputs 8-bit quantities • Decoder output: Sequence of 8-bit values • CB0, Y0, CR0, Y1, CB2, Y2, CR2, Y3… • CB (U) and CR (V) values shared between adjacent pixels • Y (brightness) value provided for each pixel Lecture 12

  8. Converting from YUV to RGB • Grab YUV value for each pixel from decoder • Y, CR, CB outputs from decoder are scaled to avoid saturation issues • Need to convert to unscaled YUV values, go from there to RGB Y(unscaled) = (255/219)(Y(from ADV) - 16) U = (127/112)( CB - 128) V = (127/112)( CR - 128) R = Y(unscaled) + 1.402V G = Y(unscaled) - 0.344U – 0.714V B = Y(unscaled) + 1.772U Lecture 12

  9. PC Display Standards • Monochrome Display Adapter (MDA) • Earliest display system for IBM PCs • Text-only – 80x25 characters, each character is 9x14 pixels • Effective resolution 720x350 @ 50 Hz, but pixels not individually addressable • IBM provided extra characters in its character set that allowed primitive graphics (boxes, lines, etc.) to be “drawn” in MDA • Hercules Graphics Card • Third-party system, adds monochrome graphics to MDA text • Color Graphics Adapter (CGA) • First mainstream color system for IBM PC • Text up to 80x25, graphics range from 640x200 in monochrome to 160x200 in 16 colors • Text displayed with lower quality than MDA (8x8 pixels/char) Lecture 12

  10. PC Display Standards • Enhanced Graphics Adapter (EGA) • 16 colors out of palette of 64 at 640x350, 80x25 text at 60 Hz • Minimum requirement for Windows 3.x • Video Graphics Adapter (VGA) • Last really accepted standard defined by IBM (consequence of IBM losing control of the “PC”) • 256 colors at 320x200, 16 colors at 640x480 • Not 256 colors at 640x480, even though that’s what most people mean when they say “VGA Resolution” • Super VGA and other formats • Much less well-defined • VESA standards developed for software compatibility between different cards Lecture 12

  11. That’s Great, Prof., but Tell us How to Make the Lab Work! • Basically, driving a VGA display involves doing the video decoder operation in reverse. • Start with a digital representation of the image • Hardware (video DAC) converts digital pixels into analog voltages used by the monitor • Different display standards have used either analog or digital signals in the past • Your hardware has to drive the control signals to the display and provide pixel values at the right rate • DAC just does conversion Lecture 12

  12. VGA Timing Lecture 12

  13. FMS3818KRC Triple DAC • Converts digital pixel data to VGA outputs Lecture 12

  14. XSGA Video DAC Lecture 12

  15. General Operation • Operation • See datasheet and XUP manual* for supported modes • *The referenced Xilinx design files won’t be provided for this lab, instead, you will replicate the behavior of the digital clock module (DCM) with FSMs in FPGA • 24-bit pixel data used to output analog signals for RGB • You are responsible for managing the timing of the VGA signal • Clock rate/time per line will give you the max number of pixels/line you can drive • Number of lines on the screen determined by ratio of time/frame and time/screen • FPGA has to drive HSYNC and VSYNC signals directly Lecture 12

  16. Driving the FMS3818KRC • CLK used to latch input registers • 8-bit pixel input bus carries color of each pixel • BLANK* signal specifies blanking interval • Assert this, don’t just drive a color that should be black • SYNC* inserts sync pulse on IOG output • Does not override any other data • Use only during blanking interval Lecture 12

  17. Making VGA Work • Generate an image in the appropriate 8-bit format • For video capture, you could use a 8-bit RGB spectrum, with 3 bits of red, 3 of green, and 2 of blue (human eyes are less sensitive to blue) • Previously, students reported they’d found routines to convert an RGB decoder output image into 8-bit format and generate the optimal palette for that image • Drive the image pixels to the triple DAC with appropriate timing signals Lecture 12

  18. Next lecture • Other Devices on the XUP Board Lecture 12

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