BEE3 Update

1. BEE3 Update Chuck Thacker John Davis Microsoft Research Chen Chang BWRC/BEECube 16 January 2008 January 2008 RAMP Retreat

2. Outline • BEE3 board properties • BEE3 gateware • BEE3 schedule January 2008 RAMP Retreat

3. Lab January 2008 RAMP Retreat

4. John explains a tricky point to Chuck January 2008 RAMP Retreat

5. BEE3 January 2008 RAMP Retreat

6. BEE3 January 2008 RAMP Retreat

7. Bandwidths (per-FPGA) • Memory • 400 MT/s * 9B/T * 2 channels: 7.2 GB/s • Ring • 500 MT/s * 9 B/T * 2 channels: 9.0 GB/s • QSH • 400 MT/s * 10 B/T: 4 GB/s • Ethernet • 125 MB/s • CX4 • 1.25 GB/s * 2 directions * 2 channels: 5GB/s • PCI Express • Same as CX4 January 2008 RAMP Retreat

8. Initial Gateware • Mostly things required for production testing and board characterization: • Signal connectivity checks • Some are AC coupled, must test at speed • QSH tested with a crossover card • Temperature and power supply monitoring • DDR-2 Controller • Useful in other designs • CX4 and PCI Express for at-speed tests • Xilinx and others have lots of IP (alas, it either doesn’t work very well, or is proprietary). January 2008 RAMP Retreat

9. Project Participants and Roles • Microsoft Research (Silicon Valley) • Funds, manages system engineering, does some gateware • Celestica (Ottawa and Shanghai) • Did main board engineering, prototype fabrication • Microsoft has a very deep relationship with Celestica • BEECube • Builds and delivers functioning systems • Function Engineering (Palo Alto) • Did thermal and mechanical engineering • Xilinx (San Jose) • Provides FPGAs for academic machines • Provides FPGA application expertise • Ramp Group (BWRC) • Control board, basic software • Ramp Community • Uses the systems for research • Expanding to industrial users (e.g., us) January 2008 RAMP Retreat

10. Bring-up Status • Most subsystems work: • Brought up a MicroBlaze on day 3 of bring-up • Ring wiring • 10 Gbit channels • Works, but requires respin to relocate MGTs • GB Ethernet • PCI Express January 2008 RAMP Retreat

11. Bring-up Status (2) • DDR2 controller doesn’t work (yet) • Largest piece of “new” IP • Works flawlessly in post-route simulation • Timing complete at 200 MHz. • Problems: • Design is complex • Six Verilog modules, including a 36-bit RISC • Design turnaround is ½ hour (i.e., tools suck). • Simulator is slow • Board testing uses ChipScope • Which doesn’t replace a ‘scope • Very difficult to probe January 2008 RAMP Retreat

12. Schedule • Generate Specification – Done • Schematic Entry – Done • Board Layout – Done • Thermal modeling, heat sink design – Done • Chassis design -- Done • Signal Integrity – Done • Board Qualification – In progress • Board Respin -- TBD • Prototypes: Spring • Production: Start Summer ‘08 January 2008 RAMP Retreat