IC-SOC Plan on Embedded Memory Defect Diagnostics and Yield Improvement

1. IC-SOC Plan onEmbedded Memory Defect Diagnostics and Yield Improvement Cheng-Wen Wu

2. Agenda (8:50-10:15) • Introduction • Cheng-Wen Wu—NTHU • Architecture & Compilation for Configurable Processors • Guoling Han/Jason Cong—UCLA • H.264 Advanced Video Codec Design • Youn-Long Lin—NTHU • Low-Power FPGA • Lei He—UCLA DTC, NTHU

3. Motivation & Purposes • Yield of on-chip memories dominates the overall chip yield • Effective memory diagnostics and failure analysis (FA) methodologies are necessary • We propose a systematic and automatic methodology for defect diagnostics • Fault pattern oriented approach • To effectively reduce candidate defects before physical FA DTC, NTHU

4. SAF0 CFid SAF1 Fault Patterns • Combining failure patterns and fault types Failure Patterns Fault Types SAF0 :00011000100 SAF1 :00100001001 CFid0:00100110001 ……. Fault Patterns DTC, NTHU

5. Diagnostics Using Fault Patterns • A cause-effect approach: Fault Patterns Defective Netlist Reduction Simulation Prediction Stage Application Stage Defect Dictionary Realistic Fault Patterns Defect Candidates DTC, NTHU

6. Realistic Defect Injection Faulty Circuits Circuit-level Simulation Simulation Results Fault Pattern Generation Fault Patterns Defect Dictionary Generation Memory Defect Diagnostics (MDD) System Design Netlist Layout Process In-Line Inspection Defect Size Cond./Distr. Fault Maps from MECA [12] Arch. RAM Spec. Scrambling Failure/Fault Pattern Analyzer Test Cond. Patterns Volt./Freq. March Dictionary Defect Candidates/Statistics AFA Defect Dictionary DTC, NTHU

7. Fault Pattern Classification DTC, NTHU

8. Overview of FFA Defect Distribution Defect Information Layout Layout Extractor CA Calculator Short defect injection Open defect injection Open Critical area calculation Short Critical Area Calculator Failure Factor Analyzer Failure Factor DTC, NTHU

9. Defect Models Particle Short Open Fault free Faulty Fault free Faulty DTC, NTHU

10. WL BL BL Gate Gnd Experiment on Industrial Designs % of Area = 114% # of Cont = 8.5 # of Via = 2 Cell A Cell B % of Area = 100% # of Cont = 8.5 # of Via = 3.5+1 Gnd Data Data Using 0.18μm CMOS Process Technology DTC, NTHU Vdd Vdd