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Chapter 2

Chapter 2. Central Processing Unit. CPU. The "brain" of the computer system is called the central processing unit . Everything that a computer does is overseen by the CPU. CPUs have for years increased their performance. CPU History.

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Chapter 2

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  1. Chapter 2 Central Processing Unit

  2. CPU • The "brain" of the computer system is called the central processing unit. • Everything that a computer does is overseen by the CPU. • CPUs have for years increased their performance.

  3. CPU History • closely tied to the IBM and Intel. The CPUs have their roots to Intel's chip 4004 from 1971. • seven or eight CPU generations up till today. • The first microprocessor to make into a home computer was the Intel 8080. • PC market moved from the 8088 to 80286 to 80386 to 80486 to Pentium, Pentium II, Pentium III and Pentium 4.

  4. Functions of CPU • executes a collection of machine instructions that tell the processor what to do. • Based on the instructions, a microprocessor does three basic things. • perform mathematical operations. • process and transfer data • make decisions

  5. The CPU – speed measurement • clock speed and data width. • Norton System Information (SI). • a relative number – 8086=1 • Computing Index (CI) – CPU Speed • Disk Index (DI) – Disk Speed • Performance Index (PI) – Combined CI & DI

  6. CPU Frequencies • The internal clock frequency is the speed inside the CPU. • The external clock frequency (Front Side Bus or System Bus) is the speed between the CPU and RAM. Internal clock frequency is higher than External clock frequency

  7. Bus & Bus Speed • connects one part of the motherboard to another. • speed measured in megahertz (MHz) • front side bus (FSB) – CPU to Northbridge. • back side bus - CPU to level 2 (L2) cache. • memory bus - Northbridge to the memory. • AGP bus - the video card to the memory and the CPU. • IDE or ATA bus - Southbridge to the disk drives. • PCI bus - PCI slots to the Southbridge.

  8. Bus Connections

  9. How does a CPU work? • centrally located on the motherboard. • data come from the RAM and other units. • receives and sends its data from and to buses. They can be divided into: • system bus, which connects the CPU with RAM • I/O buses, which connect the CPU with other components.

  10. CPU RAM L2 CACHE System Bus I/O Buses I/O UNITS (Drives, keyboard, port, adapter, etc) Bridges (Chipset) System Bus • System busis the central bus of the PC that connect CPU with RAM. • A bridgeconnects the I/O buses with the system bus and on to RAM. The bridge is part of the PC chipset. • Chip sets are a bunch of intelligent controller chips, which are on a motherboard. • Any computer will have three major system buses • Address Bus • Data Busand • Control Bus.

  11. Address Bus • Unidirectional – one direction only • carries addresses by CPU to memory and I/O elements. • The size of the address is determined by the number of lines in the bus. • The lines determine the number of memory locations and I/O, the CPU can address to.

  12. Address Bus - Example If the address bus is composed of 16 lines, the CPU will be able to generate 216, or 65,536 distinct address codes. (1k = 1024). If the address bus size is increased to a 20-bit word size, what will be the possible addresses? Possible addresses = 220 = 1,048,576 addresses

  13. Data Bus • Bi-directional – both directions. • Write operation – data from the CPU to memory. • Read operation – data moves from memory to the CPU. • size of the data bus usually corresponds to the word size of the computer.

  14. Control Bus • Bi-directional. • carries the timing and control signals. • Some are output signals orinput signals to/from the CPU to/from I/O elements. • Each microprocessor has its own unique set of control signals.

  15. Types of data • Instructions: • called program code. • include the commands send to your PC using your keyboard and mouse. • e.g. Commands to print, save, open, etc. • Data: • user data. • e.g. actual contents (the text or the letters).

  16. I/O Bus • move data. • connect all I/O devices with the CPU and RAM. • buses speed is lower than the system bus. • On modern PCs, you will usually find four buses: • The ISA bus, an old low speed bus. • The PCI bus, which is a new high speed bus. • The USB bus (Universal Serial Bus), which is a new bus. • The AGP bus (Accelerated Graphics Port) which is used for the graphics card.

  17. Physical aspects of the I/O buses • consists of tracks on the printed circuit board. • These tracks are used as: • Data • Address • Control

  18. ISA bus (Industry Standard Architecture) • Since about 1984, it is the standard bus for PC I/O functions. • ISA was an improvement over the original IBM XT bus, which was only 8 bit wide. IBM's trademark name is ATbus. • can run as 16 bit wide but it requires 2-3 clock ticks to move 16 bits of data. • ISA bus works synchronous with the CPU. • ISA bus has a theoretical transmission capacity of about 8 MB/s. (Actual speed does not exceed 1-2 MB/s.)

  19. Disadvantages of ISA Bus • narrow or limited bandwidth – only 8 bits wide • It is slow. It requires 2-3 clock ticks to move a16 bits of data. • not “intelligent”, since the CPU has to control the data transfer across the bus. • When PC communicates with the floppy drive, the rest of the PC is waiting for it to complete. • It is not in used in the new Pentium 4 computer.

  20. PCI bus (Peripheral Component Interconnect) • high speed bus of the 1990s made by Intel – 32 bit wide • is processor independent. Therefore, it can be used with all 32 or 64 bit processors. • is backward compatible with the ISA bus. • isbuffered in relation to the CPU and the peripheral components. • handles the transmission in its own tempo. • operate asynchronous. • is intelligent – All PCI adapter cards configure themselves. Plug and Play. (PnP). • is the central I/O bus, in all PCs.

  21. Plug and Play • is part of the PCI specification. It means that all PCI adapter cards are self-configuring. • During startup, communication takes place between the PC’s startup programs, the PCI controller and each PCI device (adapter). • The adapter must be able to inform the I/O bus which I/O addresses and IRQ’s it can operate with and be able to configure itself to use the resources allocated to it by the I/O bus. • When the exercise is successful, the adapter is configured automatically, and is ready to be used by the operating system. • All the components involved (adapter, motherboard and Windows) have to be Plug and Play compatible for the system to work.

  22. Schematic overview of Plug and Play

  23. Extended System Configuration Data(ESCD) • is a small data area which is stored in the motherboard’s CMOS storage. • ESCD store is used to save adapter configurationinformation; e.g. PC’s configuration. • ESCD also allows the user to manually allocate an IRQ etc. This can be done using the motherboard’s setup program.

  24. What is a chip set? • The chip sets are a bunch of intelligent controller chips; it controls the system and its capabilities. • All components communicate with the processor through the chipset transfer and organize the steady flow of data. • makes a bridge between the CPUand othercomponents. It permitted concurrent activity in all three locations, (multitasking). All data transfer to and from I/O units cross this intersection..

  25. CPU North Bridge South Bridge System Bus PCI Bus Typical Chipset

  26. MCH and ICH • a new architecture was introduced by Intel in 1999. • Memory Controller Hub (MCH) replacing the north bridge. • I/O Controller Hub (ICH) replacing the south bridge. • The MCH is a controller located between the CPU, RAM and AGP. It regulates the flow of data to and from RAM. This new architecture has two important consequences: • The connection between the two hubs is managed by a special bus (link channel), which can have a very high bandwidth. • The PCI bus comes off the ICH, and doesn’t have to shareits bandwidth with other devices.

  27. Two Bridges • a north and a south bridge. • Both bridges are essentially routers. • north bridge takes all the heavy traffic • south bridge routes in to a lot of different narrow routes

  28. Typical Chipset

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