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GORDIAN Placement

GORDIAN Placement. Perform GORDIAN placement Uniform area and net weight, area balance factor = 0.5 Undirected graph model: each edge in k -clique gets weight 2/ k. IO Placement. Necessary for GORDIAN to work. Adjacency Matrix. Shows connections among movable nodes Among nodes a to j.

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GORDIAN Placement

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  1. GORDIAN Placement • Perform GORDIAN placement • Uniform area and net weight, area balance factor = 0.5 • Undirected graph model: each edge in k-clique gets weight 2/k Practical Problems in VLSI Physical Design

  2. IO Placement • Necessary for GORDIAN to work Practical Problems in VLSI Physical Design

  3. Adjacency Matrix • Shows connections among movable nodes • Among nodes a to j Practical Problems in VLSI Physical Design

  4. Pin Connection Matrix • Shows connections between movable nodes and IO • Rows = movable nodes, columns = IO (fixed) Practical Problems in VLSI Physical Design

  5. Degree Matrix • Based on both adjacency and pin connection matrices • Sum of entries in the same row (= node degree) Practical Problems in VLSI Physical Design

  6. Laplacian Matrix • Degree matrix minus adjacency matrix Practical Problems in VLSI Physical Design

  7. Fixed Pin Vectors • Based on pin connection matrix and IO location • Y-direction is defined similarly Practical Problems in VLSI Physical Design

  8. Fixed Pin Vectors (cont) Practical Problems in VLSI Physical Design

  9. Fixed Pin Vectors (cont) Practical Problems in VLSI Physical Design

  10. Level 0 QP Formulation • No constraint necessary Practical Problems in VLSI Physical Design

  11. Level 0 Placement • Cells with real dimension will overlap Practical Problems in VLSI Physical Design

  12. Level 1 Partitioning • Perform level 1 partitioning • Obtain center locations for center-of-gravity constraints Practical Problems in VLSI Physical Design

  13. Level 1 Constraint Practical Problems in VLSI Physical Design

  14. Level 1 LQP Formulation Practical Problems in VLSI Physical Design

  15. Level 1 Placement Practical Problems in VLSI Physical Design

  16. Verification • Verify that the constraints are satisfied in the left partition Practical Problems in VLSI Physical Design

  17. Level 2 Partitioning • Add two more cut-lines • This results in p1={c,d}, p2={a,b,e}, p3={g,j}, p4={f,h,i} Practical Problems in VLSI Physical Design

  18. Level 2 Constraint Practical Problems in VLSI Physical Design

  19. Level 2 LQP Formulation Practical Problems in VLSI Physical Design

  20. Level 2 Placement • Clique-based wiring is shown Practical Problems in VLSI Physical Design

  21. Summary • Center-of-gravity constraint • Helps spread the cells evenly while monitoring wirelength • Removes overlaps among the cells (with real dimension) Practical Problems in VLSI Physical Design

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