Arithmetic II CPSC 321

1. Arithmetic IICPSC 321 E. J. Kim

2. Today’s Menu Arithmetic-Logic Units Logic Design Revisited Faster Addition Multiplication (if time permits)

3. Goals • We recall some basic logic gates • Determine the truth tables for the Boolean functions • We recall half-adders and full-adders • Ripple-carry adders • Discuss faster adders

4. Logic Gates • AND gate • OR gate • NOT gate What are the truth tables?

5. Logic Gates • NOR gate • NAND gate • XOR gate What are the truth tables?

6. Half Adder a s b c

7. Full Adder • Give a Boolean formula for s • s=cin xor a xor b • Give a Boolean formula for cout • cout =ab+cin(a xor b) • Design now a circuit using and, or, xor.

8. Full Adder cin s a b cout s=cin xor a xor bcout = ab+cin(a xor b)

9. Ripple Carry Adder

10. Critical Path cin s a b cout Suppose that each gate has a unit delay. What is the critical path (= path with the longest delay)?

11. Ripple Carry Adders • Each gates causes a delay • our example: 3 gates for carry generation • book has example with 2 gates • Carry might ripple through all n adders • O(n) gates causing delay • intolerable delay if n is large • Carry lookahead adders

12. Faster Adders Why are they called like that? cout=ab+cin(a xor b) =ab+acin+bcin =ab+(a+b)cin = g + p cin Generate g = ab Propagate p = a+b

13. Fast Adders Iterate the idea, generate and propagate ci+1 = gi + pici = gi + pi(gi-1 + pi-1 ci-1) = gi + pigi-1+ pipi-1ci-1 = gi + pigi-1+ pipi-1gi-2 +…+ pipi-1 …p1g0 +pipi-1 …p1p0c0 Two level AND-OR circuit Carry is known early!

14. Carry Lookahead Adders • Based on the previous identity • Fast because critical path is shorter • O(log n) gate delays [assuming 2-input gates] • More complex to implement • Design is less regular • Layout of one bit adder cells depend on i • Compromise • couple blocks of carry lookahead adders

15. Building an ALU • Addition • Subtraction • AND • OR • What is missing?

16. Tailoring the ALU to the MIPS • Need to support the set-on-less-than instruction (slt) • remember: slt is an arithmetic instruction • produces 1 if rs < rt and 0 otherwise • use subtraction: (a-b) < 0 implies a < b • Need to support test for equality (beq $t5, $t6, $t7) • use subtraction: (a-b) = 0 implies a = b

17. SLT • Determine a<b • Calculate b-a • If MSB equals • 1, then a<b • 0, then a>=b • Changes? • Operation less than • Output of subtraction • Overflow

18. SLT • 4 operations • subtraction output available • Connect • MSB set output • w/ LSB less

19. LSB indicates whether a<b • 0 if false • 1 if true

20. Test for equality • Notice control lines:000 = and001 = or010 = add110 = subtract111 = slt • Note: zero is a 1 when the result is zero!

21. Summary • We can build an ALU to support the MIPS instruction set • key idea: use multiplexor to select the output we want • we can efficiently perform subtraction using two’s complement • we can replicate a 1-bit ALU to produce a 32-bit ALU • Important points about hardware • all of the gates are always working • the speed of a gate is affected by the number of inputs to the gate • the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”) • We focused on basic principles. We noted that • clever changes to organization can improve performance (similar to using better algorithms in software) • faster addition, next time: faster multiplication