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Quantum Computing II CPSC 321

Quantum Computing II CPSC 321. Andreas Klappenecker. Announcements. Monday, November 29, 6:00pm-7:15pm, HRBB 113 , review session for midterm exam Tuesday, November 30, midterm exam CPSC 640 Quantum Algorithms Elephant walk. Quantum Bits. The Stern-Gerlach Experiment. Quantum Bits.

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Quantum Computing II CPSC 321

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  1. Quantum Computing IICPSC 321 Andreas Klappenecker

  2. Announcements • Monday, November 29, 6:00pm-7:15pm, HRBB 113, review session for midterm exam • Tuesday, November 30, midterm exam • CPSC 640 Quantum Algorithms • Elephant walk

  3. Quantum Bits

  4. The Stern-Gerlach Experiment

  5. Quantum Bits

  6. Memory

  7. Quantum Computing in a Nutshell

  8. Operations on a Quantum Computer

  9. Example

  10. Teleportation

  11. Teleportation – It’s Simple!

  12. Teleportation, Step by Step • Alice has two quantum bits • Bob has one quantum bit • Alice wants to teleport the state of one quantum bit • Alice and Bob share entangled bits • |00> + |11> = (1,0,0,1) normalized to length 1

  13. Teleportation – Set up

  14. Teleportation – Initial State

  15. Step 1 - XOR

  16. Step 2

  17. Rewrite State

  18. Measurement

  19. Current Research Topics

  20. Conclusion • The basic model is simple • Everyone can write a simulator of a quantum computer in a very short time • The computational model is different – you need time to absorb that! • Numerous potential technologies!

  21. Prepare for the Exam • Comprehensive Exam! • Emphasis more on newer topics • Datapath and Control • Caching • Pipelines • I/O • Multithreading • But also some older topics!

  22. Prepare for the Exam • Read the book • Chapters 5,6,7; skim through later chapters and appendices • Skim through the previous chapters 1-4 • Learn

  23. Caching • Given: A cache with some entries and a sequence of load/store instructions • Describe the evolution of the cache • When is it a hit or a miss? • What are the different eviction strategies? • LRU • Random • many others …

  24. Caching Basics • What are the different cache placement schemes? • direct mapped • set associative • fully associative • Explain how a 2-way cache with 4 sets works • If we want to read a memory block whose address is addr, then we search the set addr mod 4 • The memory block could be in either element of the set • Compare tags with upper n-2 bits of addr

  25. Implementation of a Cache Sketch an implementation of a 4-way associative cache

  26. Measuring Cache Performance • CPU cycle time • CPU execution clock cycles (including cache hits) • Memory-stall clock cycles (cache misses) • CPU time = (CPU execution clock cycles + memory stall clock cycles) x clock cycle time • Memory stall clock cycles • read stall cycles (rsc) • write stall clock cycles (wsc) • Memory stall clock cycles = rsc + wsc

  27. Measuring Cache Performance • Write-stall cycle [write-through scheme]: • two sources of stalls: • write misses (usually require to fetch the block) • write buffer stalls (write buffer is full when write occurs) • WSCs are sum of the two: WSCs = (writes/prg x write miss rate x write miss penalty) + write buffer stalls • Memory stall clock cycles similar

  28. Cache Performance Example • Instruction cache rate: 2% • Data miss rate: 4% • Assume that 2 CPI without any memory stalls • Miss penalty 40 cycles for all misses • Instruction count I • Instruction miss cycles = I x 2% x 40 = 0.80 x I • gcc has 36% loads and stores • Data miss cycles = I x 36% x 4% x 40 = 0.58 x I

  29. Pipelining • Pipeline hazards • structural hazards [hardware cannot support the combination of instructions that we want to execute during same clock cycle] • control hazards [need to make decision based on instruction that is still executing] • data hazards [instruction depends on results of a previous instruction that is still in pipeline] • Various remedies, for instance, • stall pipeline • forwarding • delayed branch block

  30. Pipelined Version

  31. Pipelining Learn how to find out dependencies using pipeline diagram Need to know the pipeline hazards inside out Q: Given a sequence of instructions, give a timing diagram [ Clock cycle | IF | ID | EX | MEM | WB ]

  32. Timing Diagrams

  33. Finding Dependencies Dependencies that go backwards in time lead to a data hazard

  34. Forwarding Data hazard: add $s0, $t0, $t1 sub $t2, $s0, $t3

  35. Stalling the Pipeline • and needs result of lw operation • hazard forces stalling of the pipeline • and and or ops need to repeat in clock cycle 4 what they did in previous clock cycle

  36. Typical Questions (Small Sample!) • Chapter 6, problems 6.2, 6.3, 6.4 • How much speed-up do you get by pipelining? • How many cycles will it take to execute this code? Problem 6.15 • Loop unrolling, problem 6.30

  37. Verilog? • I will ask little bits and pieces in mixed questions • There will be no extensive Verilog programming on paper • Little programming questions? Yes

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