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DIFFERENTIAL POLARIZATION DELAY LINE Controller FINAL REPORT PowerPoint Presentation
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DIFFERENTIAL POLARIZATION DELAY LINE Controller FINAL REPORT

DIFFERENTIAL POLARIZATION DELAY LINE Controller FINAL REPORT

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DIFFERENTIAL POLARIZATION DELAY LINE Controller FINAL REPORT

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  1. Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab DIFFERENTIAL POLARIZATION DELAY LINE ControllerFINAL REPORT D0215 Supervisor : Mony Orbach Performed by: Maria Terushkin Guy Ovadia

  2. Project Goals The ultimate goal of the project is providing digital control for the DDL

  3. DDL overview • splits light within a fiber into orthogonal polarizations • actively varies the time that one polarization travels compared to the other polarization • combines the two polarizations together again • Delay range ±50psec • Delay Resolution 0.0017 pSec

  4. Tunable laser source PC optical spectrum analyzer DDL controller Function generator Manual control Project Description • Previous usage of the DDL • Current usage of the DDL

  5. The world as we see it • DDL contains: • DC brush motor • Encoder • Limit switches -50 0 +50

  6. PC controller DDL Controller IOs • Inputs: • Encoder signals A,B • Limit indicators • Commands from PC (via USB) • Output: • PWM varying duty-cycle • Reports to PC (via USB) PWM USB Encoder feedback + limits

  7. System requirements • Maximal travel beyond the home/end indications – 2mm • Steady state error – not greater than a single encoder count • No cumulative positional error • Up to 3 sec convergence to the required set point after reaching it • No closed loop control after reaching desired position

  8. I + + - P Plant D Theoretical background • Digital PID • Continuous time domain • Discrete time domain • Where

  9. Implementation • Hardware • MMC (PCB) + Driver (wire-wrap board) • FPGA Logic • PID algorithm • Communication with PC via DLP • Software • GUI • Command line interface

  10. H bridge HIP4020 Power management Power management Hardware overview DLP USB245M transceiver Altera Cyclone transceiver transceiver wire-wrap MMC

  11. Limit protection Synchronization Debouncing Filtering Of signals Position Decoding PID homing Communication FPGA logic overview mux PWM Duty-cycle Main Controller Control lines to all blocks

  12. Application Software • Two versions: • GUI version for interactive use • Command line version for automation • Both versions save the last known delay, and load it on controller power-up.

  13. GUI Application commands • User commands • Set delay • Redefine current delay • Immediate stop • Service commands • Manual PWM override + direction control • PID constants calibration • Initiate Homing procedure • Record internal data

  14. Command line application • Contains a subset of commands useful for automation • Set delay (in pSec or encoder counts) • Load windup constant (controls speed) Compatible with VEE Pro and Matlab

  15. Discussion and conclusions • Meeting system requirements Position vs. Time go to 10 pSec 12121 encoder counts

  16. Discussion and conclusions cont. • Use of a model: • Differences between the model and the DDL and their consequences • Use of work previously done in the lab – pros and cons. • Power up • Chip safety • Implementation alternatives • Microcontroller

  17. What’s next ? • Algorithm improvement / additional features • Trajectory planning • Dual loop (velocity control) • Notch filter (mechanical resonance) • Backlash compensation algorithm • User defined software limits • Hardware improvement • Custom PCB, no wire-wrap • Tighter integration with the equipment at the EO lab • Automatic zero detection / calibration

  18. Demonstration – EO lab. • Short demonstration: • Homing procedure • “go to” 20 pSec delay position • Return to 10 pSec • Find zero manually and set it there • Power off the controller • Turn back on – last known position is retrieved

  19. The enD Just follow the yellow optical fiber ! (to the land of OZ optics)