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CGS 3269

CGS 3269. Pipelining. Pipelining – Load Store. Instruction. Fetch. Execute. 2 Stages. Fetch Mar  PC MDR  IM[MAR] Fetch Unit IR  MDR PC  PC + 1 Decoder  IR.OP. IM. MAR. IR. Exec A  R1 B  R2 ALU  A (op) B C  ALU (results)

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CGS 3269

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  1. CGS 3269 Pipelining

  2. Pipelining – Load Store Instruction Fetch Execute

  3. 2 Stages Fetch Mar  PC MDR  IM[MAR] Fetch Unit IR  MDR PC  PC + 1 Decoder  IR.OP IM MAR IR Exec A  R1 B  R2 ALU  A (op) B C  ALU (results) R3  C MDR

  4. Further Pipelining Instruction Fetch ID / OF Execute ID / OF: Instruction decode operand fetch

  5. 3 Stages Exec ALUop A (op) B C  ALUop R3 C Fetch Mar  PC MDR  IM[MAR] IR  MDR PC  PC + 1 ID / OF Decoder  IR.OP A  R1 B  R2

  6. 4 Stages Instruction Fetch ID / OF Exec. Write Back

  7. 4 Stages Exec ALUop A (op) B C  ALUop Fetch Mar  PC MDR  IM[MAR] IR  MDR PC  PC + 1 WB R3 C ID / OF Decoder  IR.OP A  R1 B  R2 *could have conflict with OF and WB

  8. A V2 R1 V1 C V3 R2 V2 R3 V1 B R4 R5 R6 R7 R8 R1 R3 V2 V1 4 Stages Example Register Files V3 = V1 + V2 There is a conflict in OF and WB because both are trying to access the register file R3 V3 I. M. IF OF EXEC. WB M OF WB MAR PC MDR

  9. 5 Stages Inst. Fetch ID / OF Exec. Mem WB Inst. Memory Data Memory Register File

  10. Load (5 stages) Load Reg, Adrr ID / OF Exec Mem WB IF Inst. Fetch Might Need To Offset Gets Value FromData Mem. Write Value back To Reg.

  11. Add (5 stages) ADD R3, R1, R2 IF ID / OF Exec Mem WB Inst. Fetch V1 = R1 V2 = R2 V3 gets V1 + V2 R3 Gets V3

  12. Store (5 stages) STORE Adrr, Reg ID / OF Exec Mem WB IF Inst. Fetch V1 Gets Reg Calculate Effective Address Adrr Gets V1

  13. CGS 3269 Pipelining

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