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1. Review 1 EE138 – SJSU

2. Serial and Parallel Representation • Binary information to be transmitted from one location to another will be in either serial or parallel format. • Serial format uses a single electrical conductor (and a common ground) for the data to travel on. The serial format is inexpensive because it only uses a single conductor and one set of input/output circuitry, but it is slow because it can only transmit 1 bit for each clock period. • Parallel format uses a separate electrical conductor for each bit to be transmitted (and a common ground). For example, if the digital system is using 8-bit numbers, eight lines are required. This tends to be expensive, but the entire 8-bit number can be transmitted in one clock period, making it very fast.

3. EXAMPLE 2–6 Sketch the serial and parallel representations of the decimal number 74. Given a clock frequency of 4 kHz. a) Find the time to transmit using each method. b) What is the state (1 or 0) of the serial line 1.2 ms into the transmission? Solution: 7410 = 0 1 0 0 1 0 1 02. Therefore, the increment of time at each falling edge increases by 0.25ms. Because each period is 0.25ms, 1.2ms will occur within the number 4 period, which, on the So line, is a 0 logic state.

4. Virtue and Physical Address – Imaginary and Real Memory For a computer with a 32-bit address bus, this means that the programmer may write a program assuming that 4 GB of memory physically exists. Since it is most unlikely that the computer will actually contain 4 GB of memory chips, the program may refer to a memory location that does not physically exist in the computer. We regard addresses from the microprocessor as imaginary or virtual addresses. Now, an address generated by the program would normally appear on the address pins of the microprocessor, but a virtual memory system modiﬁes the virtual address before it is actually placed on the address bus. The modiﬁed address is that of a memory location that physically exists in the computer; it is called a physical address.

5. Blocks/Pages and Page Frames Assume that the OS contains a loader program that transfers code from the disk to main memory. Further, the loader will transfer as much of the program code from the disk to main memory as will ﬁll the available space in the main memory. We now ask how and where this code is to be located in main memory. A commonly used solution is to regard program code as being divided into ﬁxed-size blocks or pages.

6. Example: Choose a block/page size of 4 KB (212). For 32-bit address (232), total page frames = 232 / 212 = 220 page frames. Each page frame begins at a physical memory address that is a multiple of 4K. For example, we regard location 8K + Y in the code as being located at offset Y within page 2, the number Y is a 12-bit number, yyyyyyyyyyyy. Writing 8K+Y in binary, we have 8K + Y = 0000 0000 0000 0000 0010 yyyyyyyyyyyy. The upper 20 bits indicate the page number, here 2, while the lower 12 bits indicate the offset within the page. One of the requirements of the virtual memory system is that it can transfer a page of task code and data from the disk to a page frame in memory. What is page frames of: 0x0000 0000 0001 0000 0000 xxxxxxxxxxxx Page 256 or address 256x4K

7. Page Tables A page of code may be transferred from the disk to any page frame in main memory. Hence, the virtual memory system must keep a record of the physical address in main memory where each page transferred from the disk is stored. We shall use a look-up table, the Page Table, which has one row, or entry, for every page in the program. Since a programmer may write the program as if all the 4 GB of memory address space is available for the program, the page table will have 220 entries.

8. In Figure 16.3(a), pages 504 to 508 of a program, which is stored on disk, are shown. In this example, the code in page 504 on the hard disk has been stored in page frame 225 in main memory, the code in page 505 is stored in page frame 227, and so on. A small part of the page table containing the physical page number where pages 504 to 508 are stored is shown in Figure 16.3(b). This shows that page 504 of the program is stored in main memory page frame 225, page 505 of the program is stored in page frame 227, and so on.

9. A program may make a request to access any memory location within the 4 GB address space. When it does so, the physical address is looked up in the Page Table as shown in Figure 16.4. Note that the lower 12 bits, the offset, is the same in both the virtual address and the physical address because page frames always start at a physical address ending with 12 zeros. The physical address is used to access the required location in main memory. For example, if the Page Table is as shown in Figure 16.3(b), and the virtual page number (bits 31–12 in the address from the microprocessor) is 504, the physical page number will be 225.

10. Since not all pages of the program may be actually stored in main memory, the P (Present) ﬂag indicates whether that page is currently in main memory or on the disk. Each program, or task, that the computer has stored in its main memory has its own Page Table. These may be stored in the main memory with the address of the start of the Page Table held in a special register within the microprocessor, called the Page Table Register. This register is loaded when the OS switches to a new task. Each time the virtual memory system transfers a page from disk into main memory, the physical page number is stored in the Page Table at the appropriate row, and the P ﬂag is set.

11. Improve access time: The calculated average access time of memory is defined as below: Let: tS : average access time of memory system tC: access time of cache tM: access time of main memory Deﬁne the hit ratio, h: h = Then, a cache hit gives access in tC while a cache miss gives access in tC+ tMsince both the cache and main memory are accessed.

12. That is, the average access time of memory system is reduced from 50 ns with no cache to 20 ns with the cache. If the hit ratio is 0.90, the average access time is 15 ns while a hit ratio of 0.98 gives an average access time of 11 ns. Clearly, the engineering challenge is to make the hit ratio as close to 1 as possible, since then the average access time approaches that of the cache memory.

13. Static Memory Systems Consider a memory consisting of 2M words of 32 bits each using 512K × 8 static memory chips. How many chips needed? 2Mx32 = 64M bits (21 address bits) 512Kx8 = 4M bits (19 address bits) 64M bits / 4 M bits = 16 chips Each column requires 4 chips to provide 2M x 8. Need 4 columns to provide 2M × 32 memory. The high-order two bits of the address are decoded to determine which of the 4 rows should be selected. The remaining 19 address bits are used to access speciﬁc byte locations inside each chip in the selected row. Each chip has a control input called Chip-select. When this input is set to 1, it enables the chip to accept data from or to place data on its data lines. The R/W inputs of all chips are tied together to provide a common Read/Write control line (not shown in the ﬁgure).

14. Static Memory Systems 1) If 2M words of 8 bits each using 512K × 8 static memory chips. How many chips needed: 2Mx8 = 16M bits 512Kx8 = 4M bits 16M bits / 4 M bits = 4 chips One column requires 4 chips to provide 2M x 8. The high-order two bits of the address are decoded to determine which of the 4 rows should be selected. 2) If 4M words of 32 bits each using 512K × 8 static memory chips. 3) If 1M words of 16 bits each using 256K × 8 static memory chips. 4) Describe a structure similar to the one in Figure 8.10 for an 8M × 32 memory using 512K × 8 memory chips. Solution: The required structure is essentially the same as in Figure 8.10, except that 16 rows are needed, each with four 512 × 8 chips. Address lines A18 −0 should be connected to all chips. Address lines A22 −19 should be connected to a 4-bit decoder to select one of the 16 rows

15. DISK DRIVE ACCESS TIME Consider a long sequence of accesses to a disk with an average seek time of 6 msand an average rotational delay of 3ms. The average size of a block being accessed is 8K bytes. The data transfer rate from the disk is 34 Mbytes/sec. (a) Assuming that the data blocks are randomly located on the disk, estimate the average percentage of the total time occupied by seek operations and rotational delays. (b) Repeat part (a) for the situation in which disk accesses are arranged so that in 90 percent of the cases, the next access will be to a data block on the same cylinder. Solution: It takes 8K/34M = 0.23ms to transfer a block of data. (a) The total time needed to access each block is 6 + 3 + 0.23 = 9.23 ms. The portion of time occupied by seek and rotational delay is 9/9.23 = 0.97 = 97%. (b) In 90% of the cases, only rotational delays are involved. Therefore, the average time to access a block is 0.9 × 3 + 0.1 × 9 + 0.23 = 3.89 ms. The portion of time occupied by seek and rotational delay is 3.6/3.89 = 0.92 = 92%.

16. Address Translation In a system with virtual memory, programs use virtual addresses so that they can access a large memory. The computer must translate these virtual addresses to find the address in physical memory. Recall that virtual memory and physical memory are divided into pages. The most significant bits of the virtual or physical address specify the virtual or physical page number. The least significant bits specify the word within the page and are called the page offset. Given a virtual memory system with 2 GB of virtual memory and 128 MB of physical memory divided into 4-KB pages. For 2-GB =231-byte virtual memory. For 128-MB =227-byte physical memory. Because the page size is 4 KB =212bytes: There are 231/212 =219virtual pages and 227/212 =215 physical pages. Physical memory can only hold up to 1/16th of the virtual pages at any given time. The rest of the virtual pages are kept on the hard drive.

17. Figure 8.21 Physical and virtual pages Virtual page 5 mapping to physical page 1. Virtual page 0x7FFFC mapping to physical page 0x7FFE, and so forth. For example, virtual address 0x53F8 (an offset of 0x3F8 within virtual page 5) maps to physical address 0x13F8 (an offset of 0x3F8 within physical page 1). The least significant 12 bits of the virtual and physical addresses are the same (0x3F8) and specify the page offset within the virtual and physical pages. Only the page number needs to be translated to obtain the physical address from the virtual address