Software Synthesis EE202A Presentation October 18, 2001

1. Software SynthesisEE202A PresentationOctober 18, 2001 Young H. Cho and Seung Hyun Kim

2. Outline • Background • HW/SW Co-design • Software Synthesis • Summary

3. Background • Embedded Software • Constrained Structure • “Simple,” Multiple Tasks • Target Architecture

4. HW/SW Co-design • Reactive Real-time System • Mixed HW/SW System • Software – Flexibility • Hardware – Performance SW HW

5. HW/SW Co-Design Formal Languages Partitioning SW Synthesis HW Synthesis Co-Simulation And Formal Verification RTOS Tasks Logic Synthesis Code Optimization Logic Optimization Board Level Prototyping

6. A C B Partitioning High-Level Design • Formal Languages • Textual Representation • Graphical Representation • Design Partitioning • Platform Resource • HW/SW Synthesis

7. A C B Software Synthesis • Goal: Optimized software from high-level specification • Issues to consider • Target hardware support • Retargetable compilers • Result: Efficient code for the target processor begin X1=TaskA(W); X2=TaskA(W); Y=TaskB(X1); result=TaskC(X2,Y); end

8. Code Generation • Static Code • Static (object) code for each tasks • Library of inline codes • Code optimization • Task Handling • Resource management • Static/dynamic scheduling • Communication

9. Task A Upsample 1 to 3 main(Samples *In) { while() { /* Schedule 2A */ for (j=0;j<2;j++) { /* inline code: Task A */ for (i=0;i<3;i++) { OutA[j*3+i]=InA[j]; } } for (k=0;k<3;k++) { /* inline code: Task B */ Reg=OutA[k*2] +OutA[k*2+1]; OutB[k]=Reg>>1; } } } for (i=0;i<3;i++) { Out[i]=In; } 3 2 (TaskA) 3 (TaskB) 2 Task B Downsample 2 to 1 Reg=In[0]+In[1]; Out=Reg>>1; High-Level Description Static Code Code Generation & Schedule Software Synthesis Example

10. Programming Models • FSM Model • Co-design Finite State Machine (CFSM) • Dataflow Models • Synchronous Dataflow (SDF) • Boolean Dataflow • Dynamic Dataflow • Processor Network • Others

11. CFSM • Extended FSM • Globally Asynchronous Locally Synchronous (GALS) • Unbiased towards HW or SW • Reactive, control-dominated systems • Size of the systems that can be mapped

12. SW Synthesis with CFSM • Software Graph (S-Graph) • Task Synthesis • Real-Time Operating System (RTOS) • Machine Code Compilation

13. BEGIN present_c = 1 false true a = ?c false true a’ := a a’ := a + 1 a’ := 0 emit_y := 0 emit_y := 1 END S-Graph • Control/Data-Flow Diagram • Directed Acyclic Graph (DAG) module simpleCFSM: input c: integer; output y; var a: integer in loop await c; if a = ?c then a := 0; emit y; else a := a + 1; end if end loop end var end module

14. Task Synthesis • Construction • Translation of transition function of CFSM • Recursively built from the reactive function • Optimization • Reordering or collapsing test nodes • Code-size estimation • Translation • Target language (e.g., C code)

15. RTOS • Scheduling • Individual CFSM • Communication Mechanisms • Set of flags • Memory mapped I/O port of the micro-controller • Polling or interrupts • Synthesis or Commercial RTOS

16. Cost/Performance Estimation • Accurate and Quick Estimation • Code size • Min/max execution time • Considerations • Code structures • System platform • Solution • Assign cost/timing parameters

17. a 1 D 2 b 1 2D 2 c SDF • Digital Signal Processing • Graphical Representation • Actors/Nodes • Directed edges • Delays • Synchrony • Consume Tokens • Produce Tokens • Fixed number of Tokens

18. Schedule/Memory • Static scheduling • Determine task buffer size • Memory efficient edge delay • Deterministic at compile time

19. SW Synthesis with SDF • Library of actor code blocks • Determine static schedule • Optimal code size • Performance • Inline code using schedule

20. Summary • HW/SW Co-design • Software Synthesis • Highly optimized code • Timing constraints • Efficient Resource Usage • Highest performance per cost • Control over implementation cost

21. Related Research • Berkeley HW/SW Co-Design Group • http://www-cad.eecs.berkeley.edu/~polis • Berkeley Ptolemy Group • http://ptolemy.eecs.berkeley.edu • CHINOOK • http://www.cs.washington.edu/research/chinook/ • VULCAN • Cadence Cierto VCC • Jeckle: the JAVA ECL compiler

22. References • A. Sangiovanni-Vincentelli, “What is software synthesis?,” Computer Design Editorial, Department of EECS, UC Berkeley, Berkeley, CA, June 1997. • Berkeley POLIS Group, “A Framework for Hardware-Software Co-Design of Embedded System,” POLIS Website, Department of EECS, UC Berkeley, Berkeley, CA, 1997. • F. Thoen, M. Cornero, G. Goosens, and H. DeMan, “Software synthesis for real-time information processing systems,” ACM SIGPLAN, Vol. 30, No. 11, November 1995. • Linkoping University HW/SW Co-design Course Website, http://www.ida.liu.se/~zebpe/codesign/, 1998. • EE249 “Design of Embedded Systems: Models, Validations, and Synthesis,” http://www-cad.eecs.berkeley.edu/~polis/class/index.html, UC Berkeley, CA. 2001. • P. Chou, and G. Borriello, “Software scheduling in the co-synthesis of reactive real-time systems,’ 31st ACM/IEEE Design Automation Conference, San Diego, CA, pp. 1-4, June 1994. ..

23. References • E. Lee, “Embedded software,” UC Berkeley ERL Memorandum M01/26, http://ptolemy.eecs.berkeley.edu/publications/papers/01/embsystems/ • F. Balarin, L. Lavagno, P. Murthy, and A. Sangiovanni-Vincentelli, “Scheduling for embedded real-time systems,” IEEE Design & Test of Computers, Vol. 15, No. 1, pp. 71-82, January-March 1998. http://ielimg.ihs.com/iel3/54/14269/00655185.pdf • S. Bhattacharyya, R. Leupers, and P. Marwedel, “Software synthesis and code generation for signal processing systems,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 47, No. 9, pp. 849-875, September 2000. • S. Bhattacharyya, P. Murthy, and E. Lee, “Synthesis of embedded software dataflow specifications,” Journal of VLSI Signal Processing Systems, Vol. 21, No. 2, pp. 151-166, June 1999.