1 / 4

Enabling Technologies for Low-Power High-Speed Networks

Enabling Technologies for Low-Power High-Speed Networks. Amir H. Banihashemi Broadband Communications and Wireless Systems (BCWS) Centre. BCWS Centre. Founded in 2000, has 17 faculty members and over 70 graduate students affiliated with it. Annual research funding ≈ $2M

helki
Télécharger la présentation

Enabling Technologies for Low-Power High-Speed Networks

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Enabling Technologies for Low-Power High-Speed Networks Amir H. Banihashemi Broadband Communications and Wireless Systems (BCWS) Centre

  2. BCWS Centre • Founded in 2000, has 17 faculty members and over 70 graduate students affiliated with it. • Annual research funding ≈ $2M • Extensive industrial and governmental collaboration: Alcatel, AT&T Labs, Bell Mobility, CRC, DRDC, IBM, Intel, Mitel Semiconductor (Zarlink), Nortel, NRC, … • International involvements: Wireless World Research Forum (WWRF) and WINNER (Wireless World Initiative New Radio) project • Interdisciplinary research • BCWS Seminar Series • Strong links to IEEE and ACM

  3. Theory and Implementation of Communication Algorithms • Advanced Error Control Coding (FEC, ARQ) • Turbo Equalization • Adaptive Coding and Modulation • Image and Video Coding and Transmission • Distributed Source/Channel Coding • Network Coding • MIMO Systems • Research Team: 7 Ph.D., 4 M.Sc. and 1 PDF • Carleton Collaborators: T. Kunz (SCE), J. Lambadaris (SCE), I. Marsland (SCE), R. Mason (Electronics), C. Plett (Electronics)

  4. Check Nodes Interconnections Variable Nodes Input/Output/Memory/DAC/RTAS Low-Power High-Speed Signal Processing • FPGA and ASIC Implementations of Communication Algorithms • Analog Signal Processing (in collaboration with Intel, patent pending) • Extremely low power • High-speed • Digital (100Gb/s, SiliconPro) • Electro-optical processing

More Related