Power Management for High-speed Digital Systems

1. Power Management for High-speed Digital Systems Tao Zhao Electrical and Computing Engineering University of Idaho

2. Motivation • Smaller CMOS process brings faster switching time and lower VDD • Power integrity: voltage noise margin becomes smaller • Power efficiency: static power consumption goes larger

3. How high is high-speed? • Options: A. >1KHz B. >1MHz C. >1GHz • It is when the passive components come in to play and even dominate the behavior of the circuits, the speed is high-speed • High-speed digital system study is a study of the behavior of passive components

4. Where are the passive circuits?

5. Where are the passive circuits? • Reduce VDD and increase VSS • The problem becomes more serious when VDD goes lower • Low impedance path between VDD and ground • All frequencies of interest have to be covered

6. How high do we have to care? • Clock frequencies • Signal Rise and Fall Time • FKNEE=

7. How high do we have to care? FCLOCK=25MHz TRISE=1ns FKNEE= =500MHz

8. Field Programmable Processing Array • 32-bit reconfigurable data processor, always a slave • Maximize throughput, minimize control • Multiple chips can be tiled to extend the size of the data path • Current revision: 250nm process, 250K gates, runs at 25MHz, radiation-hardened • 16 pairs of power and ground pins

9. Reconfigurable Memory Module • Serves as memory for the FPPA • Include memory address control and 1MB RAM • Like the FPPA, multiple RMMs can be tiled too • RMM has only been simulated in software, but not been fabricated • Assume the RMM has the same DC characteristics as the FPPA

10. The Reconfigurable Platform

11. Power Domain

12. Power Budget • DC characteristic • Target impedance

13. Power Delivery Path

14. Voltage Regulator Linear vs. Switching

15. Voltage Regulator Linear Voltage Regulator Switching Voltage Regulator • low efficiency • low noise level • cheap • high efficiency • high noise level • expensive • Supply desired voltage level • Supply enough current • Radiation hardened

16. Wiring Impedance • Wiring Resistance is negligible • V=L*di/dt

17. Decoupling Capacitor (Decap)

18. Bulk Capacitor • ESL • Self-resonant frequency

19. Parallel Ceramic Capacitors • Self-resonant at higher frequency • parallelism

20. Ceramic Capacitor Selection

21. Ceramic Capacitor Array

22. Ceramic Capacitor Array

23. Decoupling Capacitor Network

24. Dynamic Power Management • Subsystems can be powered up and down in runtime • High-side load switch

25. Power-up Challenge • Free from big current spike, monotonic voltage ramp-up • Don’t upset the rest of the system • Decoupling capacitor network adds load capacitance: internal capacitance (nF); decap (μF) • Inrush current: I=C*dV/dt • I=C*dv/dt=5 μF*2.5V/1 μs=12.5A

26. Soft Start-up • Small dV/dt rate substantially reduces inrush current • Soft start: longer time, less current • The rise time of the gate voltage determines the turn-on time of the PMOS

27. Slew-rate Controllable High-side Load Switch

28. Reduce Inrush Current

29. Sequencing and Voltage Supervisor • Commercial products -- ADM1066 Programmable Sequencer • 10 channels for sequencing and 12 channels for supervising • Contain a state machine to control the sequencing and supervising

30. Conclusion • High-speed digital design focuses on the behaviors of passive circuits • Digital system design trends: lower VDD requires better power integrity and power efficiency

31. Conclusion Design flow: • Power budget • Choose the right voltage regulator • Design decoupling capacitor network to filter voltage noise • Use soft-start and sequencing start-up to prevent big inrush current • Voltage supervisor

32. Future Work • Measurement: accurate numbers • Board level interconnection: LVDS • Lower voltage: Better power integrity

33. Acknowledgement • Dr. Gregory Donohoe • Dr. Kenneth Hass • Dr. Robert Rinker • All the FPPA team members

34. Thank you! Questions?