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High Speed Digital Design Project

High Speed Digital Design Project. SpaceWire Router. By: Asaf Bercovich & Oren Cohen Advisor: Mony Orbach Semester: Winter 2007/2008 2-Semester Project Date: 19 November 2007. Project Goal. Designing a SpaceWire Switch Core (Router) compatible to ECSS-E-50-12A Standard.

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High Speed Digital Design Project

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  1. High Speed Digital Design Project SpaceWire Router By: Asaf Bercovich & Oren Cohen Advisor: Mony Orbach Semester: Winter 2007/2008 2-Semester Project Date: 19 November 2007

  2. Project Goal • Designing a SpaceWire Switch Core (Router) compatible to ECSS-E-50-12A Standard. • The design will be coded and simulated using Xilinx development enviroment and implemented onto a Xilinx VirtexII-Pro FPGA.

  3. Router Specifications • 4 – Ports (Possibly only 3 depending on the FPGA constraints) • Supporting multiple sessions on a given moment. • Implementation of “Path-Addressing” + Header Deletion. • Wormhole Routing. • A minimum rate of 2MBit/Sec full duplex.

  4. System Topology Station Station Router Station Station

  5. Transmitter State Machine Receiver A Simplified SpaceWire Port Dout TX DATA / Control Sout Clock Reset Din RX DATA / Control Sin

  6. Simplified Datapath

  7. 4 3 2 Cargo EOP Path-Addressing Example

  8. Time Schedule • SpaceWire Port design milestones • 20.11.07 – 24.11.07 Port Transmitter Design. • 25.11.07 – 01.12.07 Port Receiver Design. • 02.12.07 – 8.12.07 Port State Machine Design. • 9.12.07 – 15.12.07 Integration and testing. • Presentation of a SpaceWire Port.

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