High Speed Digital Design Project

High Speed Digital Design Project SpaceWire Router Midterm Presentation By: Asaf Bercovich & Oren Cohen Advisor: Mony Orbach Semester: Winter 2007/2008 2-Semester Project Date: 7 January 2008

Project Goal • Designing a SpaceWireSwitch Core (Router) compatible to ECSS-E-50-12A Standard. • The design will be coded and simulated using Xilinx development enviroment and implemented onto a Xilinx VirtexII-Pro FPGA.

System Topology Router

System Topology • Full duplex • Low latency • Point-to-point • Wormhole Routing • Asynchronous communication • Automatic failover • 800 Mb/s of Traffic Total Router PORT

SpaceWire Characters • There are only 5 Characters: FCT – “Flow Control Token" ESC – “Escape” EOP – “End Of Packet” EEP – “End of Packet with Error” NCHAR – “Normal Character”

The SpaceWire Port Architecture Entity TX Clock Write Ready Dout Read Ready FIFO Transmitter Sout TX DATA / Control Reset HOST OUTER WORLD Port Controller Link Start / Link Disable Clock State Machine Read Din Ready Write FIFO Ready Receiver Sin RX_CLOCK RX DATA / Control

The SpaceWire Port Architecture TX Clock Write Ready Dout Read Ready FIFO Transmitter Sout TX DATA / Control Reset HOST OUTER WORLD Port Controller Link Start / Link Disable Clock State Machine Read Din Ready Write FIFO Ready Receiver Sin RX_CLOCK RX DATA / Control

Internal Signals Transmitter RESET Send NULLs Send FCTs Send N-Chars Send Time-Codes Port Controller (State Machine) GotFCT Got Time-Code GotN-Char GotNULL CreditError RX_Err RESET Receiver

Port Controller Q Q Q D D D Flip Flop Flip Flop Flip Flop R R R Synchronization Example Controller Logic ‘1’ RX_Err Controller’s Clock Asynchronous Reset Synchronizer

Port Transmitter“The Factory” TX DATA Shift Register Control Signals TX Clock Controller SpaceWire Character Logic Logic Logic Dout DS Encoder Sout

Port Receiver RX Clock Recovery Error Reporting Sequence Detector + Data Extraction RX_DATA to FIFO MEM Din Shift Register Rx Clock Din Sin

RX Clock Recovery Version I – XOR Gate D RX_CLOCK S D S RX_CLOCK

RX Clock Recovery Version II - Quad Data Rate Flip Flop RX_CLOCK Q D D S D S RX_CLOCK

RX Clock Recovery D S RX_CLOCK Version III – Three DDR Flip Flops & XOR Gate

RX Clock Recovery DDR FF DDR FF DDR FF RX_CLOCK Q Q Q D D D D S Version III – Three DDR Flip Flops & XOR Gate better RX_CLOCK

Project Milestones Semester Goal – Port Completion • 8-14/1/08 – Assimilation of FIFOs into Port’s architecture. • 15-21/1/08 – Checking feasibility for 200 MHz work frequency (using DCM module). • 22/1–11/2/08 – Testing & Stabilization of Port’s final design. • 12/2-25/2/08- Gathering information about routing with SpaceWire.

References • ECSS-E-50-12A - 24 January 2003

High Speed Digital Design Project