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High Speed Digital Systems Lab June 2008

A cceleration of E conomic C alculation. Black & Scholes model Acceleration. Developers: Ayal Ozer and Eyal Efrat Mentor: Michael Yampolsky. High Speed Digital Systems Lab June 2008. Acceleration of Economic Calculation Agenda. Overview and reminder Interface Architecture and SW

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High Speed Digital Systems Lab June 2008

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  1. Acceleration of Economic Calculation Black & Scholes model Acceleration Developers: Ayal Ozer and Eyal Efrat Mentor: Michael Yampolsky High Speed Digital Systems Lab June 2008

  2. Acceleration of Economic Calculation Agenda • Overview and reminder • Interface • Architecture and SW • Problems we’ve encountered • Solutions • Timetable

  3. Acceleration of Economic CalculationOverview • The B&S formula estimates the value of an option • Using specialized hardware could accelerate the calculation time of the B&S value by a factor of hundreds

  4. Acceleration of Economic CalculationThe interface

  5. Acceleration of Economic CalculationArchitecture AEC SW Input from server Output to GUI Financial Server Local Server Regular software calculation B&S input B&S input B&S input B&S input B&S input B&S input B&S input B&S input

  6. B&S B&S B&S Acceleration of Economic CalculationArchitecture Arbitrator Arbitrator Input table from B&S SW Output table to B&S software

  7. Acceleration of Economic CalculationProblems • The Logarithm function • Floating point

  8. Acceleration of Economic CalculationPossible solutions • Taylor series • Embedded core: NIOS II • Look Up Table

  9. B&S Combinatorical Logic Acceleration of Economic CalculationArchitecture revised/continued B&S black-box diagram Input Output Distribution table & Lan LUT

  10. Acceleration of Economic CalculationTime Table

  11. Acceleration of Economic Calculation Questions?

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