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High Speed Digital Systems Lab Final presentation NOV 2011 Instructor: Rolf Hilgendorf

Integration of an A/D Converter into the sub-Nyquist Xampling system. High Speed Digital Systems Lab Final presentation NOV 2011 Instructor: Rolf Hilgendorf Students: Elad Mor , Ilya Zavolsky. Part A Accomplishments. Design of transmission test environment.

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High Speed Digital Systems Lab Final presentation NOV 2011 Instructor: Rolf Hilgendorf

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  1. Integration of an A/D Converter into the sub-Nyquist Xampling system High Speed Digital Systems Lab Final presentation NOV 2011 Instructor: Rolf Hilgendorf Students: EladMor, IlyaZavolsky

  2. Part A Accomplishments A/D Integration Design of transmission test environment. Performing speed tests to receive the highest frequency for valid transmission (Loop-Back). Design and testing of A/D & NI adapters. Design of advanced VHDL testing environment for the A/D adapter. Execution of a single channel and a full width transmission (A/D->Adapter->StratixIII) [without performance of the bitslip or word alignment operations].

  3. Part B Goals A/D Integration To define and implement the synchronization stages of 8 differential channels/48-bit data streams (DPA, CDA, WAM). To estimate the link quality using an automated error detection mechanism. To understand the serial configuration interface of the A/D, and to design an automatic/manual controller. To design of the relevant hardware components and to integrate them to form the final design. To test and analyze the sub-blocks and the integrated system.

  4. A/D Integration

  5. Bitslip8: Performs channel-by-channel data alignment. The same hardware is used for all 8 channels, through a mux/demux selection.The state machine will change each channel’s word boundary, until it matches the transmitted word (“111000”). A/D Integration

  6. WAM: Word Alignment Mechanism; Implemented in order to solve channel-to-channel skew. After switching to WAM stage (mux_select=“10”),and transmission of all-zeros in all channels, The trigger has to be asserted. Its rising edge is clearing the main FF, and then the incoming data should change to all-ones. Then the FF will sample the LSB of every channel to determine which of the channels are late. Then by this result , The MUX array is selecting between the incoming data and a delayed version of it and re-synchronizing the channels by that. A/D Integration

  7. WTPG - WAM Test Pattern GeneratorWas designed according to the same principle that guided us in the design of WAM. The decision vector is given from the user. At the assertion of the trigger signal, the data is changing from all-zeros to all-ones, with the effect of the delay of the channels that correlating bits were asserted in late_chan_vec[7..0]. A/D Integration

  8. Full Width transmission combined with bitslip8 and WAM (stm2) and WTPG – WAM Test Pattern Generator A/D Integration

  9. LFSR background LFSR usage and designation in stm3 The goal of the stm3 design is to perceive a Packet Error Rate (PER) estimation, over a long period of time, for the LVDS interface and Stratix3 receiver module. Therefore, following the instructor's advice we have used a 32-bit Fibonacci LFSR generator and checker. They were connected at receiver and transmitter ends of the design. The LFSR Generator: TDG_Y_BUS The generator is based on a 32 bit LFSR extended to 48 bits. When enabled and started, the circuit produces a pattern shifted by one bit each cycle. The circuit operates at the basic clock rate at 60MHz. After bit 48 becomes 1 the first time, a self-holding latch is set to give a data_valid output signal to enable the circuitry. A/D Integration LFSR (Linear Feedback Shift Register) is a shift register whose input bit is a linear function of its previous state. Applications of LFSRs include generating pseudo-random numbers, with the big advantage of generating all of the possible sequences (except one).

  10. Link Quality testing through LFSR error detection design (stm3) – Receiver block diagram A/D Integration The LFSR Checker: TDC_Y_BUS Test-data generated by 32 bit LFSR and extended to 48 bit is compared with incoming data. The LFSR structure is identical to the one in TDG_Y_BUS; however, this LFSR may be loaded parallel with data. Each cycle, the complete received data is loaded into a compare-register. Then the outputs of the compare-reg and the shift-reg are tested for equality. The errors are counted externally.

  11. A/D Serial Control development • Looking into the A/D manual to learn the serial control interface. • Experimenting with the A/D Serial configuration control interface (TCM) to perceive different configuration and test patterns. • In TCM we have discovered errors in the pin assignment on the ADA which had to be fixed by creating bypasses on the adapter. • Characterization of the Serial control interface for the final design: • Response time • Defining the order of action for the initialization of the A/D • Undefined output for a single cycle (X) A/D Integration

  12. Design of the final A/D Controller: • Development of the controller according to the principles of operation that were learned in TCM. • Implementation of Automatic/Manual configuration options (Manual- through external control regs) • Build of an interface between the A/D controller and the ProcWizard GUI and the Slave state machine (which is in charge of the initialization). A/D Integration

  13. Testing of the final design • Offset testing: • Maximum measured on channel D: 15 mV (Specified maximum offset). • Rest of the channel shown approximately 2 mV offset which is the specified typical offset. A/D Integration • Waveform analysis: • Spikes phenomena eventually attributed to reflection caused by bypassing the ADA. • Disconnection of the stumps has fixed the problem.

  14. As apparent, the final outcome of this test showed higher gain levels than expected. A/D Integration • Gain test: • Peak-to-peak amplitude voltage gain was not unity as measured, and also seem to be frequency dependant. • The analog inputs on the A/D card are connected to the A/D chip through two coils (unbalanced to balanced). Looking into these transformers data sheet revealed a characteristic frequency response.

  15. Final test – feeding the A/D with NI generated signal that was mixed in Mishali’s MWC Result: The a2di design is fully operational! A/D Integration

  16. Future improvements A/D Integration • ADA card revision: pin reassignment according to Gidel’s IC4 layout. • Trigger addition. • GUI control interface. • Gain distortion correction • Custom A/D card renovation • Gain correction through FFT data representation • Integration with the Expander

  17. Questions / Answers Thank you! A/D Integration

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