Digital Systems Design Lab

1. Digital Systems Design Lab TA : 曾興嘉 sjzeng@viplab.cs.nctu.edu.tw

2. Lab Requirements • Write Hardware Description Language (HDL) • Verilog • The verilog code must: • be able to be synthesized • pass the patterns • Basic Requirements: 70% of the grades • Competing with others: 30% of the grades

3. Lab Schedule • 3 Labs • Lab1: Key Arithmetic Units (5%) • Date: 3/29~4/13 • Lab2: Sequencing and Control Circuits (5%) • Date: 4/13~5/4 • Lab3: Simple RISC Central Processing Units (10%) • Date: 5/4~6/8 • Late submission: • one week from due date: 60% • more than one week: 0%

4. EnvironmentSetup • The software must run on workstations based on linux distribution because of the license issue. • The users can use Pietty to telnet to the workstation and acquire windows-like interface via Xming. • Tool • Pietty • http://ntu.csie.org/~piaip/pietty • Xming • http://sourceforge.net/projects/xming

5. EnvironmentSetup (Xming) No Access Control • Open Xming

6. EnvironmentSetup (Pietty) • Server: 140.113.241.168

7. Set X11 Forwarding in Pietty

8. FTP

9. Basic Unix Commands • cpfile1.v file2.v • Make a copy of file1.v called file2.v • cp~/dir1/file1.v . • Make a copy of ~/dir1/file1.v in your current directory • “.” means your current directory • “~” means your home directory • rmfile1.v • Delete file1.v • mkdirdir1 • Make a new directory called dir1 • cddir1 • Change the current directory to dir1 • cd.. • Change the current directory to the upper directory • morefile1.v • View the content of file1.v • ls • List all the files in the current directory • pwd • Display the name of the current directory

10. Cell-based Design Flow Overview A design flow is a set of procedures that allows designers to progress from a specification for a chip to the final chip implementation in an error-free way.

11. Source: CM: 5086 VLSI Design Lab Cell-based Design Flow Specification Development System Models System Architecture Stage 1 Implement your own verilog program Need to pass the provided testbench Synthesis your logic with provided (or modify by yourself) tcl file RTL code development Functional Verification RTL Synthesis Timing Verification Synthesis Stage 2 Use your(provided) netlist file to run the Auto Place and Route (APR) flow Physical Synthesis/Place and Route Physical Verification Physical Design Prototype Build and Test System Integration and Software Test

12. Cell-based Design Tool • System Architecture/SW simulation • C/C++, Matlab, System C, System Verilog… • RTL simulation/debug • NC-Verilog, NC-VHDL, ModelSim, Verdi(nWave)… (without delay) • Synthesis • RTL Compiler, Design Compiler , Power Compiler… • Gate level simulation/debug • NC-Verilog, NC-VHDL, ModelSim, Verdi(nWave)… (with delay) • Physical Design • SoC Encounter, Astro, IC Compiler… • Others • PrimePower , Calibre, Nanosim…

13. RTL Simulation • Development / simulation • NC-verilog • ncverilog + <your_testbench_file> • ncverilog TESTBED.v +access+r

14. RTL Waveform • Check the simulation output • Dump waveform from testbench when simulation • fsdbDumpfile(“MAC.fsdb”); • nWave • nWave &

15. RTL Schematic • Verdi from NOVAS • Verdi & • File->Import Design ->From File ->Seq_MAC16.v ->Add ->OK

16. Source: CIC Jan.08 Design Compiler Synthesis Residue = 16’h0000; If(high_bits==2’b10) residue = state_table[i]; Else state_table[i] = 16’h0000; Translate(HDL Compiler) HDL Source(RTL) Optimize + Map (Design Compiler) NO Timing Info => Generic Boolean Timing Info => Target Technology • Synthesis=translation+ optimization+ mapping

17. Synthesis • Design Compiler • It synthesizes your designs (Verilog) into optimized technology-dependent, gate-level designs. • Use Design Compiler GUI • tartup xming ( or any other X terminal application) • design_vision (dv)

18. Synthesis • Environment Setup • /home directory/.cshrc : set path and license of synthesis tool • /your working directory/.synopsys_dc.setup : setup technology file, designware library file…etc • Use DC-TCL script file(.tcl) • Set design constraints • dv -f syn.tcl

19. Synthesis Put the “RTL file”, “.synopsys_dc.setup” and “syn.tcl” to your working directory, or assert the setup commands by hand, while synthesis. Under your working directory, make new directories, Report and Netlist, for saving synthesis reports.

20. Synthesis command Command return result(error) command Command return result(done) Output result

21. Synthesis Report timing.txt The synthesis information is in your “Report” directory

22. Gate Level Waveform • Check the simulation output • nWave • nWave &

23. Gate Level Schematic • Verdi from NOVAS • Verdi & • File->Import Design -> From File -> Netlist/Seq_MAC16_SYN.v ->Add -> /cad/designkit/CBDK_IC_Contest_v2.0/Verilog/tsmc13_neg.v ->Add -> OK

24. Verilog Basic Module module module_name(port_name); port declaration data type declaration task & function declaration structure or module functionality endmodule

25. Lexical Convention • Number Specification • <size>’<base><value> • <size> is the length in bits • <base> can be b(binary), o(octal), d(decimal) or h(hexadecimal) • <value> is any legal number in the selected base • e.g. 8’d11 = 8’b00001011 = 8’h0b • e.g. 12’hz = zzzz zzzz zzzz (high impednace) • e.g. 6’bx = xx xxxx (unknown value)

26. Lexical Convention • Operators • Arithmetic Description • A = B + C; • A = B – C; • A = B * C; • A = B / C; • A = B % C; • / and % are not supported in most synthesis tools. • Shift Operator (bit-wise) • A = B >> 2; // shift right ‘B’ by 2-bits • A = B << 3; // shift left ‘B’ by 3-bits

27. Lexical Convention • Operators • Bit-wise operator • A = ~B; // not • A = B & C; // and • A = B | C; // or • A = B ^ C; // xor • e.g. 4’b1001 | 4’b0101 => 4’b1101 • Logical operators (return 1-bit result) • A = !B; • A = B && C; • A = B || C; • e.g. 4’0101 || 4’b1101 => 1’b1

28. Lexical Convention • Operators • Conditional Description • if else • case endcase • C = sel ? A : B; //if(sel==1’b1) then C=A, else C=B • Relational and equality(conditional) • <=, <, >, >=, ==, !=

29. Lexical Convention • Operators • Concatenation • { }=> a = {b, c}; • {{}}=> a = {2{c}}; • a[3:0] = {d[2:0], 1’b0};

30. Data Type • Declaration Syntax • <data_type> [<MSB>:<LSB>] <list_of_identifier> • <data_type>: There are two groups of data types: “register” and “net” in Verilog. • e.g. wire temp; // 1-bit net • e.g. reg temp; // 1-bit register • e.g. wire [7:0] temp; // 8-bits bus, temp[7] is the MSB • e.g. wire [0:7] temp; // 8-bits bus, temp[0] is the MSB • e.g. reg [4:0] temp; • e.g. reg signed [4:0] temp; • e.g. wire signed [7:0] temp;

31. Port • Port declaration • input : input port • output : output port • inout : bidirectional port

32. Module Connection • 1. connected by port order • MAC16 Com_MAC(REG_IN1,REG_IN2,REG_OUT,OUT); • 2. connect by name • MAC16 Com_MAC(.a(REG_IN1),.b(REG_IN2),.c(REG_OUT),.out(OUT));

33. Sequential Logic always@(posedge clk or posedge reset) always@(negedge clk) always@(posedge clk) begin if(reset) qout<=1’b0; else qout<=din; end

34. Combinational Logic 1. wire a,b,sel,out; assign out=(sel)?a:b; 2. wire a,b,sel; reg out; always@(a or b or sel) begin if(sel) out=a; else out=b; end

35. Combinational Logic a b out c d Full case always@(a or b or c or d or num) begin case(num) 2’d0: out=a; 2’d1: out=b; 2’d2: out=c; 2’d3: out=d; endcase end

36. Combinational Logic a b out c d Latch add Default: out=a; can avoid latch Incomplete case always@(a or b or c or d or num) begin case(num) 3’d0: out=a; 3’d1: out=b; 3’d2: out=c; 3’d3: out=d; endcase end