Digital Systems Design

1. Shyue-Kung Lu Department of Electronic Engineering Digital Systems Design

2. Syllabus Recommended Texts 1. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL,” Prentice Hall (新月圖書) References 1. Richard S. Sandige, “Digital Design Essentials,” Prentice Hall (開發圖書) 2. John F. Wakerly, “Digital Design: Principle and Practices,” Prentice Hall (新月圖書) 3. M. Morris Mano, “Digital Design,” Prentice Hall, Third Edition (滄海書 局，04-27088787) 4. M. Morris Mano, :Digital Logic and Computer Design Fundamentals,” Prentice Hall (新月圖書) Grades 1. 作業 25% 2. 期中考 30 % 3. 期末考 30% 4. Project 15% Project 以歷屆 FPGA 比賽題目為主

3. Course Overview • Review of combinational and sequential logic design • Introduction to synthesis with HDLs (Verilog HDL) • Programmable logic devices (CPLD and FPGA) • State machines, datapath controllers, RISC CPU • Architectures and algorithms for computation • Synchronization across clock domains • Static Timing Analysis • Fault simulation and testing, JTAG, BIST Digital Systems Design

4. Chapter 1-3Review of Digital Systems

5. Logic Level Ranges of Voltage for a Digital Circuit

6. + out b a Representations of a Digital Design Z = A' •B' •(C + D) = (A' •(B' •(C + D))) Logic expression True table Transistor circuit Gate netlist

7. Basic Primitives

8. Some Common IC Gates

9. Typical IC Datasheet

10. Combinational Logic Circuit • Combinational circuit: logic circuit whose outputs at any time are determined directly and only from the present input combination. • A combinational circuit performs a specific information-processing operation fully specified logically by a set of Boolean functions. • Sequential circuit: one that employ memory elements in addition to (combinational) logic gates—their outputs are determined from the present input combination as well as the state of the memory cells.

11. Combinational Circuit n inputs m outputs Fig. 4-1: Block Diagram of Combinational Circuit Block Diagram of a Combinational Circuit

12. Combinational Modules • Ripple Carry Adder • Carry Look ahead Adder • Binary Adder-Subtractor • BCD Adder • Magnitude Comparator • Binary Multiplier • Decoder/Encoder • Priority Encoder • Multiplexers/Demultiplexers • Three-State Gates

13. Sequential Circuits

14. Synchronous Clocked Sequential Circuit

15. Clock Response in Latch and Flip-Flop

16. Setup time and Hold Time

17. DFF

18. JKFF

19. JKFF

20. Characteristic Tables and Equations • Q(t + 1) = D (D Flip-Flop) • Q(t + 1) = JQ’ + K’Q (JK Flip-Flop) • Q(t + 1) = TQ’ + T’Q (T Flip-Flop)

21. DA = A  x  y

22. Mealy Machine Outputs dependent on inputs and state variables. Are inputs synchronized with clock?

23. Input Output State Registers Comb. Circuit Comb. Circuit Outputs dependent on state variables only. Moore Machine

24. A register is a group of flip-flops, read/written as a unit. A register that goes through a prescribed sequence of states upon the application of input pulses is called a counter. 4-Bit Register

25. 1 0 1 0 I0 I0 0 1 1 0 I0 I0 I0 0 0 1 0 1 I1 I1 0 1 I1 I1 I1 0 0 1 I2 I2 1 0 0 1 1 0 I2 I2 I2 0 1 0 1 0 0 1 I3 I3 I3 I3 I3 0 Register withParallel Load

26. Shift Register 1 0 1 0 1 1 0 1 0 Edge trigger or level trigger?

27. No need to go through a sequential logic design process. The flip-flop in the least significant position is complemented with every pulse. A flip-flop in any other position is complemented when all the bits in the lower significant positions are equal to 1. Synchronous Counter