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Group Meeting July 21, 2009

Group Meeting July 21, 2009. Justin Burkhart. Presentation Outline. More Exact Analysis of Class E Resonant Boost Converter Gate Drive Options Transistor Layout Optimization. Boost Converter Operation . Switch is opened and closed periodically

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Group Meeting July 21, 2009

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  1. Group Meeting July 21, 2009 Justin Burkhart

  2. Presentation Outline • More Exact Analysis of Class E Resonant Boost Converter • Gate Drive Options • Transistor Layout Optimization

  3. Boost Converter Operation • Switch is opened and closed periodically • The rectifier LC tank is assumed to have high Q such that the current in L2 is purely sinusoidal • L1 and C1 are tuned such that when the switch is opened, the voltage across the switch will ring back to zero half of a period later

  4. Delivery of Power + + - - Pinv Pout Pin Inverter (lossless) Rectifier (lossless) Vin Vout Pin = Pinv = Pout

  5. Delivery of Power + + - - Iin-dc+I1sin(wt)+I2sin(2wt)+… Pinv Pout Pin Inverter (lossless) Rectifier (lossless) Vin Vout Pin = Pinv = Pout Pin=VinIin-dc

  6. Delivery of Power + + - - Iout-dc+Io1sin(wt)+Io2sin(2wt)+… Iin-dc+I1sin(wt)+I2sin(2wt)+… Pinv Pout Pin Inverter (lossless) Rectifier (lossless) Vin Vout Pin = Pinv = Pout Pin=VinIin-dc Pout=VoutIout-dc

  7. Delivery of Power + + - - Iinv-dc+I1-invsin(wt) Iout-dc+Io1sin(wt)+Io2sin(2wt)+… Iin-dc+I1sin(wt)+I2sin(2wt)+… Pinv Pout Pin Inverter (lossless) Rectifier (lossless) Vin Vout Pin = Pinv = Pout Pin=VinIin-dc Pinv=PAC+PDC Pout=VoutIout-dc

  8. Inverter: Detailed Analysis wo,zo Unknowns: wo, zo, IAC, o1, IL(0) Constraints:<IL(t)> = Pout/Vin,<VC(t)> = VIN,<VC’(Ts/2)> = 0, 0.5 VC-Fund IAC cos(o-o1) = Pout(1-Vin/Vout) Known Initial Conditions: Vc(0)=0

  9. Inverter: Detailed Analysis wo,zo Unknowns: wo, zo, IAC, o1, IL(0) Constraints:<IL(t)> = Pout/Vin,<VC(t)> = VIN,<VC’(Ts/2)> = 0, 0.5 VC-Fund IAC cos(o-o1) = Pout(1-Vin/Vout) Known Initial Conditions: Vc(0)=0 Solve system of non-linear equations for each value of wo

  10. Rectifier: Detailed Analysis Unknowns: wr, zr, ton, toff Constraints:<VD(t)> = VIN, <IL(t)> = POUT/VOUT, IAC and o1 are constrained by the inverter Known Initial Conditions: VD(toff) = VOUT, IL(toff) = 0

  11. Rectifier: Detailed Analysis Unknowns: wr, zr, ton, toff Constraints:<VD(t)> = VIN, <IL(t)> = POUT/VOUT, IAC and o1 are constrained by the inverter Known Initial Conditions: VD(toff) = VOUT, IL(toff) = 0 Solve system of non-linear equations

  12. Gate Drive Options Hard Switched Gate Drive Loss arises from charging and discharging CISS through a resistor every cycle. Thus, loss is proportional to switching frequency. Since the converter is operating at 75 MHz this loss can be substantial, however, this scheme has very low complexity. Resonant Gate Drive An inductor can be added in series with the gate to form a resonant circuit with CISS. This essentially charges and discharges CISS with a sinusoidal current. Loss occurs in RISS.

  13. Introduction to TI’s LBC5 Process Removed

  14. LDMOS Layout Removed

  15. LDMOS Layout Optimization • Large LDMOS transistors are formed by connecting many smaller transistors in parallel • Optimization serves to find the total device size, finger size, finger layout, and metal layout that achieves the highest converter efficiency • Loss Model:

  16. Scaling of Parasitics Removed

  17. Optimization Procedure • Sweep total device width • Sweep number of fingers • Calculate loss • Choose total device width and number of fingers • Find best aspect ratio and top metal layer layout

  18. Optimization Result (Hard Switched) Solid Lines: Ross set by scaling measured data Dashed Lines: Ross set as 3 Rds

  19. Optimization Result (Hard Switched) Solid Lines: Ross set by scaling measured data Dashed Lines: Ross set as 3 Rds Choose 45000um and 100 Fingers

  20. Optimization Result (Resonant Gating) Solid Lines: Hard Switched Dashed Lines: Resonant Gating

  21. Choose Aspect Ratio • Total Area Available: 1500x1000 um • Finger Cross Section: 13.8 um • Finger Width: 245 um

  22. Choose Aspect Ratio • Total Area Available: 1500x1000 um • Finger Cross Section: 13.8 um • Finger Width: 245 um 3 rows is chosen

  23. Top Metal Design

  24. Top Metal Design Metal 1 Gate

  25. Top Metal Design Metal 1 Metal 2 Source

  26. Top Metal Design Metal 1 Metal 2 Drain

  27. Top Metal Design Metal 1 Metal 2 Source Drain

  28. Taper Angle Optimization • Adjust the size of the network based on the number of fingers per row and solve for equivalent resistance using MATLAB Voltage Vector Constant Vector Node Matrix

  29. Taper Angle Optimization Optimization ignores metal resistance in connecting rows

  30. Device Layout

  31. Ideas for Improvement? Break long rows into multiple columns

  32. Ideas for Improvement? Metal 1 Metal 2 Gate

  33. Ideas for Improvement? Metal 1 Metal 2

  34. Ideas for Improvement? Metal 1 Metal 2 Source

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