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GTS Issues & Status M. Bellato

GTS Issues & Status M. Bellato. AGATA Week – GSI 21-24 Feb 2005. GTS Hierarchy. GTS Functionality - Downlink. GTS Functionality - Uplink. GTS Components – ATCA crate. GTS Components – Fanin Fanout board. GTS Components – Mezzanine. Work in Progress on:. GTS mezzanine

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GTS Issues & Status M. Bellato

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  1. GTS Issues & StatusM. Bellato AGATA Week – GSI 21-24 Feb 2005

  2. GTS Hierarchy

  3. GTS Functionality - Downlink

  4. GTS Functionality - Uplink

  5. GTS Components – ATCA crate

  6. GTS Components – Fanin Fanout board

  7. GTS Components – Mezzanine

  8. Work in Progress on: • GTS mezzanine • Phase equalization algorithm • Atca fanout board • Vhdl development • SystemC simulation

  9. GTS Mezzanine • Pcb layout entirely redone at Cern • Fixes manufacturing problems • Signal integrity analysis on critical nets • New functionalities added

  10. GTS Mezzanine layout

  11. Alignment Algorithm • Two models • Phase equalization by consecutive MGT resets • Phase equalization by direct measurements

  12. Mezzanine Tx MGT Opt Fiber Rx Root tx Root rx Consecutive MGT resets Root node GTS clock

  13. Consecutive MGT resets • Mgt wakes up with arbitrary phase • Almost uniformly distributed in one clk cycle • At the root node the phase of RXUSRCLK is the sum of downstream and upstream MGT pairs clk phases • Idea : minimize or maximize this sum • The contribution of each pair almost equal • By halving the measure we obtain the latency of each pair

  14. TEST CONDITIONS P1 100 MHz OSC “ROOT” “NODE” RECOV. CLOCK 100m FIBRE DATA PATTERN TX1 RX2 RDOUT CLK SHIFTER / FILTER RDOUT CLK RX1 TX2 DATA OUT RocketIO MGT RocketIO MGT DATA P2 P3 oscilloscope ASYMMETRY = |TD-TU| / 10 [ns] NUMBER OF MEASURES = 11481 TD TU TL

  15. DOWN-LINK LATENCY DISTRIBUTIONS (TD)

  16. UP-LINK LATENCY DISTRIBUTION (TU)

  17. LOOP LATENCY DISTRIBUTION (TL)

  18. ASYMMETRY vs LOOP LATENCY

  19. Direct Measurements Mezzanine Tx MGT Opt Fiber Rx Select

  20. Atca Fanout Board • Rapid testbed for VHDL development • Used as fanin-fanout & root node • Programmable • Customizable area • Provided by Xilinx & Avnet

  21. Vhdl Development • Standalone GTS Mezzanine • Needed for LLP testing • Needed for Ancillary I/F testing • Functionalities • Global clock and timestamp • GTS I/F protocol compliant • Validates all trigger requests

  22. Simulation • SystemC environment • Behavioural model of different parts of LLP system, included the GTS mezzanine • It’s very first use will be as reference for Vhdl coding. • Ongoing development at Strasbourg, Orsay and Padova

  23. Time plan • GTS mezzanine tested & (hopefully) delivered in the next two months • Fanout board adaptation in Q2-05 • Prototype system integration in Q1-06

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