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Digital Design

Digital Design. Jeff Kautzer Univ Wis Milw. Review: Digital Information. Information is represented numerically using a binary number system An n bit number has digit weightings 2 (n-1) 2 (n-2) 2 (n-3) ……. 2 1 2 0 Example: 11010b = 2 4 + 2 3 + 2 1 = 26

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Digital Design

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  1. Digital Design Jeff Kautzer Univ Wis Milw

  2. Review: Digital Information • Information is represented numerically using a binary number system • An n bit number has digit weightings 2(n-1) 2(n-2) 2(n-3) ……. 21 20 • Example: 11010b = 24 + 23 + 21 = 26 • 4 bit binary “nibbles” are abbreviated using hexidecimal • 1001b = 9h, 1010b = Ah, 1011b = Bh, ….. 1111b = Fh • Logic 1: Represented by a high voltage level and/or forward current • Logic 0: Represented by a low voltage level and/or reverse current • Binary numbers are conveyed individually in time between two or more digital devices. • Devices have electrical limitations in drive, speed, distance, & fanout • Devices may share the same wires/nodes using time based multiplexing

  3. Review: Basic 2 Input Logic Operators Gates and their Demorgan Equivalents Note: A Bubble implies logic inversion

  4. Review: Basic 2 Input X-OR Operators & Gates

  5. Review: Truth Tables, Karnaugh Maps N = 4 Grey Code

  6. Example: Binary-7Segment Display Decoder 2 Types of Display Configurations Vcc Common Cathode LEDS Active High Common Anode LEDS Active Low Gnd

  7. 7 Segment Display 7- segment used to form digits 0-9

  8. Commercial TTL BCD-to-7-segment decoder/driver driving a common-anode 7-segment LED display; 7447 segment patterns for all possible input codes.

  9. Truth Table for Active High (Common Cathode Display Drive) Hex Digits A-F not defined by this decoder. All Segments OFF

  10. Truth Table Reduction • Two lines can be combined if the same output is obtained but the input variable values differ in only 1 bit position. • The variable for which the value differs with no effect on output is eliminated from the resulting expression. D C B D C B C B A D C B

  11. Combining Adjacent Cells (Min Terms) Reduces Logic Implementation a = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD Karnaugh Map Combinations AC BD • 8 Min Terms …. 8 Input OR Gate • Min Term = 4 Input AND Gate (plus ~4 Inversions) • ~ 10 Gates ACD CD

  12. Additional Segment Maps

  13. Liquid-Crystal Displays Liquid-crystal display: (a) basic arrangement; (b) applying a switching voltage between the segment and the backplane turns ON the segment. Zero voltage turns the segment OFF.

  14. Commerical Logic devices for driving an LCD segments and full 7-segment displays

  15. Common XOR Reduction Patterns (Alternating Columns, Quads, and Pairs, Checkerboards)

  16. Digital IC Technologies/Families • Bipolar: Utilizes BJT’s exclusively as switching elements. Originated by Fairchild/TI, families have included STD, L, H, LS, S, ALS, AS and F • pp74xxx###P Standard Part Numbering Scheme Package Suffix (Plastic, Ceramic, DIP, SOJ, etc) Generic Device Function Number (Ex. 244 Octal Driver) Family Designation (Ex. ALS, AS, F, etc) 7 =Commercial (0-70C), 5 =Military (-55 to 125C or more) Mfg Prefix (Ex. SN = Texas Inst, DM = Fairchild, etc) Example Function/Family Package Options For Family Examples see: http://focus.ti.com/logic/docs/logicportal.tsp?templateId=5985&DCMP=TIHomeTracking&HQS=Other+OT+home_p_logic

  17. C B E • Review: Schottky Diode • PN Junction Si Diode Similar to std diode • Low Forward Voltage Drop (~0.3V) • Schottky Transistor • Schottky Diode from Collector to Base of NPN switching transistor • Vbc < Vf of Schottky Diode (~0.3V) • Vce-sat (schottky) > Vce-sat (std BJT) • Base-Collector Clamp prevents hard saturation • Switches Faster as a result

  18. Digital IC Technologies/Families • CMOS: Utilizes C-MOSFETs exclusively as switching elements. Originated with 4000 series family (still produced) followed with C, HC, HCT, AC, ACT, FCT, LV & LVC • Devices follow Bipolar part numbering scheme (except for 4000 series) • Characterized by • Very low input current (leakage current) • Symmetric Output drive currents • Device size/process scales. Industry has moved from 5um channels to less than 100nm channels in < 30 yrs Example: HC, HCT Families Function/Family Package Options

  19. Other Digital IC Semiconductor Technologies • BiCMOS: Combination CMOS/BJT. Can be implemented using Si but SiGe becoming popular for mixed signal applications. Families include: BC, BCT, FBT, ABT, ALB, & LVT • ECL/LVDS: Emitter Coupled Logic / Low Voltage Differential Signaling. Si BJT or CMOS devices that utilize differential signaling with extremely low voltage swings. Typically seen on the output from A/D conversion circuits. Switching speeds > 60Mhz. • GaAs: FET based devices with extremely fast switching and delay characteristics. Ft > 10Ghz easily achievable. Costs > 20X that of fast CMOS

  20. Other Aspects of Technology:Component Life Cycle Phases • = Mean (Max) Sales of Unit Components per Unit Time s = One Standard Deviation in Sales/Time

  21. Life Cycle of a Component • Special Histogram of Production as Measure by Component Sales/Time (# shipped/time) • Concept Assumes Component Sales follow monotonically increasing to peak, then monotonically decreasing to obsolesence • Life Cycle is Measured Relative to Peak of Sales • +/- 1s from Peak = Mature Product • -1s to –2s from Peak = Growth Product • -2s to –3s from Peak = Introductory Product • +1s to +2s from Peak = Declining Product • +2s to +3s from Peak = Phase Out Product • +3s and higher from Peak = Obsolete Product • Limitations of Product by Demographics, Geographics • Cautions and Warnings • Compatibilities or Incompatibilities • Specific Label Applications or Misapplications • Safety Rules

  22. Life Cycle of Common Analog IC’s as predicted in late 1990’s

  23. Life Cycles of IC Processes

  24. Life Cycles of IC Process Voltages

  25. Life Cycle Phases of IC Packages

  26. Sustainability Aspects: Obsolescence • For each component in a BOM, consider life cycles • Example: Consider the previous LCP Data • Type (only for analog IC’s) • Process • Package • Voltage • For each Aspect, Find u+(2.5)s, u+(3.5)s dates • Use u, s in years • +2s to +3s from Peak = Phase Out Product • +3s and higher from Peak = Obsolete Product • Find worst case values (earliest of the four categories) • Create a separate IC BOM table of obsolescence analysis with above data • ID all parts above the 2.5s, Separately ID all above 3.5s

  27. Obsolescence Table Example • Sample calculations for a few suspect IC’s (Present Date p = 2000.8) • In this case, the present date was subtracted from the window points and any negative value means there is a potential issue

  28. Logic Signal Electrical Characteristics • Finite Transition Time Zone • Driver must switch voltage thru this zone within specified time or risk causing linear operation of receiver ! • Typically < 1uS but varies with logic family technology

  29. Logic Device Drive Parameters Note: Sourced currents are always listed as a negative number by convention on data sheets

  30. Interpreting the Data Sheet Vih, Vil Ioh, Iol Voh @ Ioh (note max Ioh) Vol @ Iol (note max Iol) Iih, Iil

  31. Device Output Structure Type 1: Totem Pole Current Limiting Resistor (reduced in modern devices) Top Voh/Ioh Source Driver (Switch to Vcc) Bottom Vol/Iol Sink Driver (Switch to Gnd) Cross-over of Q4:Q5 – ON/OFF may result in high current spike from Vcc to Gnd Octal and larger devices rated for “Gnd Bounce” Volp. Measure of Static output disturbance when all other outputs switch simultaneously.

  32. Device Output Structure Type 2: Open Collector/Drain • Current Limiting Resistor Removed • Top Voh/Ioh Source Driver Removed • Bottom Vol/Iol Sink Driver • Sink Trans Q5 acts as a switch to Gnd • No inherent Logic 1 voltage drive • Interface in 2 ways; • Pullup resistor to Vcc to establish logic 1 voltage level • Switch current through load device (Ex. Relay Coil, LED, Lamp, Solenoid, etc) Note OC/OD Datasheets: May list Vce-sat for Vol, Ic max for Iol max, Vce max (off). Will NOT list Voh, Ioh values ! OC/OD Outputs will have very slow Logic 0 to 1 transition times !

  33. OC/OD outputs may be tied together, Wire-OR Determining Pullup Resistor Limits • Maximum R - Limited by Logic 1 condition: R must supply Vih @ Iih to receiver plus supply any leakage current to the driver OFF transistors. Finite Current of Io flows thru R dropping voltage. Usually use R < 100KW • Minimum R - Limited by Logic 0 condition: Driver ON may cause Vol as low as 0V, Driver must sync Io from Vcc thru pullup resistor plus Iil source current from receiver. Total load current cannot exceed Driver Iol current capacity. Usually use R> 1KW

  34. Device Output Structure Type 3 Tristateable Current Limiting Resistor (reduced in modern devices) Top Voh/Ioh Source Driver (Switch to Vcc) Bottom Vol/Iol Sink Driver (Switch to Gnd) Q7/Q8 used to stop base current to Q3/Q4 darlington Turn off Source Driver Q2 used for same purpose but controls Sink Driver E turns OFF Q4 and Q5 simultaneously

  35. Interpreting the Data Sheet Vcc Supply Voltage Range Normal Input Specs apply to Enable Input (G) Off State Output Leakage Currents Logic Level Dependent Icc Max Supply Current Note: Occurs when outputs in Hi Z

  36. Multiplexing Drivers for Bus Operation • Active Driver must provide Iih/Iil currents to ALL receivers plus all the OFF state leakage currents of the other inactive Drivers • Must NOT have 2 or more Drivers Active simultaneously. Time Division multiplexing (timing) analysis critical to long term reliabililty of devices

  37. Standard vs Schmitt Trigger Input Functions • Single Input Threshold Vth, Eliminates Undefined Transition Zone • Input should also have minimum “hysteresis” to provide noise immunity • As Vin increases thru Vth, Vth decreases by DV (Vhyst) • As Vin decreases thru Vth, Vth increases by DV (Vhyst) • Vth is typically 1.0 – 2.0 V, Vhyst should be > 200mV • Schmitt Trigger should always follow OC/OD outputs or other slow rise or fall time signals (Ex. Optocoupler Outputs, RC Reset Circuits, etc )

  38. Basic Combinatorial Timing Parameters • TpHL(TpLH): Propagation Delay from High to Low (Low to High) Logic Level Usually measured between the 10% and 90% total voltage transition points. • Tpd or Tp: Propagation Delay usually stated as worst case of TpHL and TpLH. • Tott or Tout: Output Transition Time. For many families (HC, HCT, etc), gate delays are stated with separate specifications for logical output value generation (Tpd) plus physical output voltage transition (Tott). Need to sum these for total prop delay !! • TpzH(TpzL): Propagation Delay from High Impedance to High (Low) Logic Level • TpHz(TpLz): Propagation Delay from High (Low) Logic Level to High Impedance

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