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Digital Design Concepts

Digital Design Concepts. Xilinx Distributor Certification Program Module 1 Digital Design Concepts. Congratulations! You now sell programmable logic semiconductors. Any idea what they are?. Be sure to view this presentation in PowerPoint “Notes Page” to see speaker notes.

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Digital Design Concepts

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  1. Digital Design Concepts Xilinx Distributor Certification Program Module 1 Digital Design Concepts Congratulations! You now sell programmable logic semiconductors. Any idea what they are? Be sure to view this presentation in PowerPoint “Notes Page” to see speaker notes.

  2. Agenda Keywords you will learn semiconductor silicon transistor integrated circuit discrete semiconductor transistor digital device gate flip flop interconnect standard logic PLD CPLD FPGA gate array standard cell full custom ASIC I/O gate vs I/O limited propagation delay system frequency • Semiconductors • Integrated Circuits • Digital Logic Basics • Logic Device History • Basic Concepts • Quiz

  3. Semiconductors Total Semiconductors $160.1B (1999) Actual 1999 worldwide semiconductor sales: Source: Dataquest $160,100,000,000

  4. Semiconductors: scientific semiconductors: Can be conductor OR insulator, located at boundary of the two Insulators: Do not conduct electricity Metals: Conduct electricity

  5. The Transistor ON Apply current here And the switch is on! Defn: 3 terminal semiconductor device that acts as a digital switch.

  6. Semiconductor Categories Total Semiconductors $160.1B (1999) ICs Discretes 130.2 29.9 • Discrete Devices • A single transistor or diode • Customized for special needs (e.g. power) • Optoelectronics included in this category • Integrated Circuit (IC) • A bunch of transistors on a single piece of silicon • More complex functions (e.g. a Pentium has 10 million transistors)

  7. Integrated Circuits Total Semiconductors $160.1B (1999) ICs Discretes 130.2 29.9 Digital DevicesAnalog 108.9 21.3 • Digital Devices • Operate at only 2 levels: 0 or 1 • Very precise way to store & manipulate data • Easy to miniaturize • Analog Devices • Operate using a wide dynamic range of voltages • More difficult to control compared to digital • Susceptible to noise • Necessary for interface to the real world 1 0

  8. Digital Devices Total Semiconductors $160.1B (1999) ICs Discretes 130.2 29.9 Digital Devices Analog 108.9 21.3 Logic Micros Memory 28.3 52.3 28.3 1 byte • Memory • DRAM • SRAM • FLASH • MicroComponents • Microprocessors • Microcontrollers • Peripherals • Digital Logic! address data stored or retrieved

  9. ON ON 1 1 1 1 1 0 ON OFF What’s a gate? • Fundamental building block for digital logic • Simple gates consist of 4 to 6 transistors • A measure of a digital device’s capacity • How a 3-input gate works ... If your customer places an order AND ... Then you will get your commission! ON Xilinx ships the product AND ... ON 0 1 ... your boss doesn’t fire you

  10. Types of gates Xilinx Gates AND2 AND2B1 AND2B2 AND3 AND3B1 AND3B2 AND3B3 AND4 AND4B1 AND4B2 AND4B3 AND4B4 AND5 AND5B1 AND5B2 AND5B3 AND5B4 AND5B5 AND6 AND7 AND8 AND9 OR2 OR2B1 OR2B2 Gates come in all different flavors: AND gate OR gate NAND gate XOR gate There are over 800 different gates in the Xilinx library!

  11. D Q > What’s a flip-flop? Xilinx Flip Flops FD FD4 FD8 FD16 FD_1 FD4CE FD4RE FD8CE FD8RE FD16CE FD16RE FDC FDC_1 FDCE FDCE_1 FDCP FDCPE FDP FDP_1 FDPE FDPE_1 FDR FDRE FDRS FDRSE • A circuit used to store digital information • Consists of 6 - 9 gates • Used in counters, registers and state machines • Number of flip-flops in a device is important for designers during the selection process Simple Flip-Flop DATA input output (no idea why Q) CLOCK input

  12. 1 1 1 0 0 0 How a flip-flop works Xilinx Flip Flops FDS FDSE FDSR FDSRE FJKC FJKCE FJKCP FJKCPE FJKP FJKPE FJKRSE FJKSRE FTC FTCE FTCLE FTCP FTCPE FTCPLE FTP FTPE FTPLE FTRSE FTRSLE FTSRE FTSRLE Flip-Flop Timing Diagram 1 0 D Q > DATA OUTPUT 0 CLOCK transition A transition B DATA CLOCK OUTPUT go! go! time

  13. Digital Logic HistoryStandard Logic Devices Total Semiconductors $160.1B (1999) ICs Discretes 130.2 29.9 Digital Devices Analog 108.9 21.3 Logic Micros Memory 28.3 52.3 28.3 Std Logic 2.6 • Introduced in the late 60’s • Multiple gates in a single package! • Aliases: SSI, MSI, TTL, LS, DTL, RTL • Major players today: Philips, TI, National • Gives design flexibility to connect individual “chips” off the shelf saving lots of time • Big opportunity for distributors to sell lots of different parts! the black outline is the IC package, this one 16 pin Dual Inline Package (DIP) 4 - 50 gates

  14. Logic Interconnect • Method to hook-up gates inside a single device • Need to have enough to connect most gates • Too much will mean a big die size & high cost vertical interconnect A B used interconnect path horizontal interconnect gates

  15. D Q > D Q > D Q > D Q > Digital Logic HistoryS PLD - Simple Programmable Logic Device Total Semiconductors $160.1B (1999) ICs Discretes 130.2 29.9 Digital Devices Analog 108.9 21.3 Logic Micros Memory 28.3 52.3 28.3 Std Logic SPLD 2.6 0.16 • Developed in the late 70’s • Major players today: AMD, Lattice, Cypress • First device that needs software • First device that needs a programmer gates flip flops interconnect A very common low cost IC package has pins on all 4 sides called a Plastic-Leaded Chip Carrier (PLCC) 50 - 200 gates

  16. Digital Logic HistoryGate Array Total Semiconductors $160.1B (1999) ICs Discretes 130.2 29.9 Digital Devices Analog 108.9 21.3 Logic Micros Memory 28.3 52.3 28.3 Std Logic S PLD Gate Array 2.6 0.16 3.0 Defn: An integrated circuit with an array of transistors which can be connected by metal interconnect during the fabrication process. gates interconnect To increase the number of I/Os, the pin thickness and spacing (pitch) are dramatically reduced in this Thin Quad FlatPack package (TQFP). 1,000,000+ gates

  17. Digital Logic HistoryGate Array Total Semiconductors $160.1B (1999) ICs Discretes 130.2 29.9 Digital Devices Analog 108.9 21.3 Logic Micros Memory 28.3 52.3 28.3 Std Logic S PLD Gate Array 2.6 0.16 3.0 • The ultimate lego set for digital designers • Advantages • Very dense (today over 1,000,000 gates) • Fast performance • Very low unit cost • Disadvantages • Long turn around time (8-10 weeks) • $20-100k engineering charges/design • Risk, if it’s wrong you start again, pay again! • Major players: Fujitsu, NEC, Toshiba, LSI

  18. Digital Logic HistoryStandard Cell Total Semiconductors $160.1B (1999) ICs Discretes 130.2 29.9 Digital Devices Analog 108.9 21.3 Logic Micros Memory 28.3 52.3 28.3 Std Logic S PLD Gate Array Standard Cell 2.6 0.16 3.0 12.1 • Similar to gate array but much more flexible • Advantages: • More optimized die size compared to GA • Cheaper device price compared to GA • Can add analog functions • Disadvantages: • No standard, more $ engineering ($50k+/design) • Requires 100k+ units/year • Much longer development time • Much higher risk • Major players: Lucent, LSI, TI

  19. Digital Logic HistoryFPGA - Field Programmable Gate Array Total Semiconductors $160.1B (1999) ICs Discretes 130.2 29.9 Digital Devices Analog 108.9 21.3 Logic Micros Memory 28.3 52.3 28.3 Std Logic S PLD FPGA Gate Array 2.6 0.16 1.6 3.0 Defn: An array of logic cells with general interconnect that is under the user’s control. logic cells interconnect 2k - 125k gates

  20. 0 1 1 0 0 1 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 0 1 1 1 1 1 Digital Logic HistoryFPGA - Field Programmable Gate Array LUT flip flop Total Semiconductors $160.1B (1999) ICs Discretes 130.2 29.9 Digital Devices Analog 108.9 21.3 Logic Micros Memory 28.3 52.3 28.3 Std Logic S PLD FPGA Gate Array Standard Cell 2.6 0.16 1.6 3.0 12.1 2 types of FPGAs • Reprogrammable (SRAM-based) • Xilinx, Altera Flex, Lucent, Atmel • SRAM determines interconnect • SRAM defines logic in Look Up Table (LUT) • One-time Programmable (OTP) • Actel, Quicklogic • Interconnect is anti-fuse • Logic is traditional gates SRAM logic cell gates flip flop OTP logic cell

  21. Digital Logic HistoryCPLD - Complex Programmable Logic Device Total Semiconductors $160.1B (1999) ICs Discretes 130.2 29.9 Digital Devices Analog 108.9 21.3 Logic Micros Memory 28.3 52.3 28.3 Std Logic S PLD CPLD FPGA Gate Array 2.6 0.16 0.8 1.6 3.0 Defn: A hybrid of PLD blocks and gate array interconnect for mid-size logic designs. macrocells interconnect 500 - 5k gates

  22. Digital Logic HistoryCPLD - Complex Programmable Logic Device Total Semiconductors $160.1B (1999) ICs Discretes 130.2 29.9 Digital Devices Analog 108.9 21.3 Logic Micros Memory 28.3 52.3 28.3 Std Logic S PLD CPLD FPGA Gate Array Standard Cell 2.6 0.16 0.8 1.6 3.0 12.1 • Technology introduced late 80’s by PlusLogic • Vendors: Altera (MAX), Lattice, Cypress, Vantis, Xilinx • 2 Primary Technologies • EEPROM (old technology) • FLASH (new technology - used by Xilinx CPLDs) • FPGAs vs CPLDs • FPGAs have much greater capacity • CPLDs are faster for some small applications • Both are easy to design • The customer’s design will dictate the logic solution

  23. SPLD FPGA CPLD Standard Logic Standard Cell Full Custom Gate Array Digital Logic HistorySummary Design Capacity (gates) 1M+ Programmable Logic 125k 5k 200 Logic 28.3 Std Logic SPLD CPLD FPGA Gate Array Standard Cell Full Custom 2.6 0.16 0.8 1.6 3.0 12.1 8.2 3% -8% 13% 28% -17% 22% -28% 1999-2004 CAGR Development Time hours days weeks months years

  24. Basic ConceptsI/Os - Inputs and Outputs Types of I/O Buffers Input Output Tri-state Bi-directional Input Latch Output Latch Input Register Output Register Input Pullup Output Pullup Hi Slew Output TTL Input TTL Output CMOS Input CMOS Output • All signals on & off chip must go through I/O buffer • User can choose many I/O buffer options O I/O buffer I package pin silicon die

  25. Basic ConceptsGate vs I/O limited I/O limited Gate limited Logic Logic Logic Logic All I/Os are used by the design but not all gates All logic is used by the design but not all I/Os

  26. Basic ConceptsPropagation Delay (tPD) Fractions of a second .001 = 1 mili (ms) .000001 = 1 micro (us) .000000001 = 1 nano (ns) Defn: The time required for a signal to travel from A to B, measured in nanoseconds (ns). Gate Delay Net Delay tPD = 3ns tPD = 1ns

  27. Basic ConceptsPath Delay Defn: The sum of all the gate and net delays from starting to ending point. fanount=2 tPD = 3ns tPD = 1.2ns tPD = 3ns tPD = 1.8ns tPD = 3ns Path Delay = sum of all gate + net delays = 3ns + 1.2ns + 3ns + 1.8ns + 3ns = 12ns

  28. 1 fMAX = longest flip-flop path delay D Q > tPD = 2ns tCQ = 2.5ns tPD = 1ns tPD = 0.5ns tPD = 2ns Basic ConceptsMaximum System Performance (fMAX) Circuit Events per Second 1 = 1 Hertz (Hz) 1,000 = kilo (kHz) 1,000,000 = mega (MHz) 1,000,000,000 = giga (GHz) Defn: The fastest speed a circuit containing flip-flops can operate, measured in Megahertz (MHz). fMAX = 1/(flip-flop delay + gate delays + net delays) = 1/(2.5 + 1 + 2 + 0.5 + 2)ns = 1/(8ns) = 125 MHz

  29. Module 1 Quiz Xilinx Distributor Certification Program Module 1 Digital Design Concepts Congratulations! You now should have mastered the basics of digital design. To complete this module, you need to visit your local Rep office and do the Module 1 quiz. It is a closed-book, multiple choice quiz of 25 questions. If you understand the material presented here, it will be a snap. If you’re not certain about some areas, ask the instructor for clarification now! A B C D E

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