1. Chapter 7Memory Hierarchy

2. Outline

3. Technology Trends

4. Processor Memory Latency Gap Time of a full cache miss in instructions executed • 1st Alpha: 340 ns/5.0 ns = 68 clks x 2 (136 instr.) • 2nd Alpha: 266 ns/3.3 ns = 80 clks x 4 (320 instr.) • 3rd Alpha: 180 ns/1.7 ns =108 clks x 6 (648 instr.)

5. Solution: Memory Hierarchy Speed: Fastest Slowest Size: Smallest Biggest Cost: Highest Lowest

6. Memory Hierarchy: Principle

7. Why Hierarchy Works?

8. How Does It Work? Speed (ns): 1’s 10’s 100’s 10,000,000’s 10,000,000,000’s (10’s ms) (10’s sec) Size(bytes): 100’s K’s M’s G’s T’s

10. How Is the Hierarchy Managed?

11. Memory Hierarchy Technology

12. Memory Hierarchy Technology

13. Memory Hierarchy: Terminology

14. 4 Questions for Hierarchy Design

15. Memory System Design

16. Summary of Memory Hierarchy

17. Outline

18. Basics of Cache

20. Hits and Misses

21. Hits and Misses

22. Avoid Waiting for Memoryin Write Through

23. Exploiting Spatial Locality

25. Block Size Block Size Tradeoff

26. Memory Design to Support Cache

27. Interleaving for Bandwidth

28. Cache Performance

29. Improving Cache Performance

30. Reduce Miss Ratio with Associativity

31. Set-Associative Cache

32. Possible Associativity Structures

33. Block Placement

34. Data Placement Policy

35. Cache Block Replacement

36. Comparing the Structures

37. A 4-Way Set-Associative Cache

39. Reduce Miss Penalty with Multilevel Caches

40. Sources of Cache Misses

41. Cache Design Space

42. Cache Summary

43. Outline

44. Virtual Memory

45. Virtual Memory

46. Why Virtual Memory?

47. Basic Issues in Virtual Memory

48. Paging

49. Key Decisions in Paging

50. Choosing the Page Size