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Delay Fault Simulation with Bounded Gate Delay Model

Delay Fault Simulation with Bounded Gate Delay Model. Soumitra Bose Design Technology, Intel Corp. Folsom, CA 95630 Hillary Grimes and Vishwani D. Agrawal Dept. of ECE, Auburn University Auburn, AL 36849. Purpose. Investigate min-max delay simulation used for process variation

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Delay Fault Simulation with Bounded Gate Delay Model

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  1. ITC-07 Paper 26.3 Delay Fault Simulation with Bounded Gate Delay Model Soumitra Bose Design Technology, Intel Corp. Folsom, CA 95630 Hillary Grimes and Vishwani D. Agrawal Dept. of ECE, Auburn University Auburn, AL 36849

  2. ITC-07 Paper 26.3 Purpose • Investigate min-max delay simulation used for process variation • Improve upon existing min-max delay simulation • Determination of fmax (VTS’07) • Determination of delay fault detection (this paper)

  3. ITC-07 Paper 26.3 Outline • Background • Min-max Delay Simulation • Determination of fmax • Hazard Lists • Fault Detection • Correcting the detection threshold • Finding fmax vs Fault Detection • Results

  4. ITC-07 Paper 26.3 Definitions • Guaranteed failure frequency (fmax) • This is the lowest clock frequency above which all (even the fastest) circuits will fail. Testing at fmax will show a failure if a delay fault, detectable by the vectors, exists (Bose et al., 1993). • Gate delay fault • Assume that a delay fault is lumped at a faulty gate (Pramanick & Reddy, ITC’88) • All other gates have their delays within the specified (min, max) range.

  5. ITC-07 Paper 26.3 Min-Max Delay Simulation 1/fmax 0 1 3 3 5 1,3 1,3 1,3 1,2 4 11 1,2 1,2 2 5 1 1 3,4 1,3 1,3 1,3 5 9

  6. ITC-07 Paper 26.3 Reconvergent Fanout Analysis Fall occurs at time ‘x’ Hazard cannot occur 0 1 x 3 3 5 1,3 1,3 1,3 1,2 4 6 11 1,2 1,2 x+1 5 1 1 3,4 1,3 1,3 1,3 Output rises at least 1 unit after ‘x’ 5 9

  7. ITC-07 Paper 26.3 Determination of fmax 1/fmax 0 1 3 3 5 1,3 1,3 1,3 1,2 4 6 11 1,2 1,2 2 5 1 1 3,4 1,3 1,3 1,3 5 9

  8. ITC-07 Paper 26.3 Hazard Lists • Hazard Lists generated at fanout points contains • originating fanout name • ambiguity interval • Propagate hazard lists through downcone of fault site • similar to fault lists in concurrent fault simulation

  9. ITC-07 Paper 26.3 Hazard List Propagation • Hazard lists at the inputs of a reconvergent gate help determine its output • If signal correlations are such that no hazard can occur, the hazard is suppressed • Otherwise, the hazard lists are propagated to the gate’s output, and ambiguity intervals are updated

  10. ITC-07 Paper 26.3 Fault Detection • We want to make sure the fault is detected • Propagating hazard lists allows signal correlations to be used • More accurate fault detection and detection threshold calculations

  11. ITC-07 Paper 26.3 Detection Threshold Threshold = 8 0 1 3 3 5 1,3 1,3 1,3 1,2 4 11 1,2 1,2 2 5 1 1 3,4 Tc = 12 1,3 1,3 1,3 5 9

  12. ITC-07 Paper 26.3 Corrected Detection Threshold Threshold = 6 0 1 3 3 5 1,3 1,3 1,3 1,2 4 6 11 1,2 1,2 2 5 1 1 3,4 Tc = 12 1,3 1,3 1,3 5 9

  13. ITC-07 Paper 26.3 Finding fmax vs Fault Detection • A circuit output may have multiple ambiguity regions 4,6 0 3,4 0 4 6 7 10 3 4

  14. ITC-07 Paper 26.3 Finding fmax • Determination of fmax finds the leading transition of the last ambiguity region that occurs 4,6 0 3,4 0 4 6 7 10 3 4 1/fmax

  15. ITC-07 Paper 26.3 Fault Detection • Fault detection finds the minimum delay that would shift the last ambiguity region to guarantee detection 4,6 0 3,4 0 4 6 7 10 3 4 Tc = 11

  16. ITC-07 Paper 26.3 Fault Detection • A faulty inverter with delay size 4 or greater is guaranteed to be detected 4,6 0 3,4 0 4 6 7 10 3 4 Tc = 11

  17. ITC-07 Paper 26.3 Fault Detection • A faulty AND gate with size between 4 and 5 is guaranteed to be detected. 4,6 0 3,4 0 4 6 7 10 3 4 Tc = 11

  18. ITC-07 Paper 26.3 Fault Detection Tc=12 4 6 7 8 11 0 4 5 4,6 4,5 0 1 4 X 1,4 0,0 3 4 2,2 1,4 3 6 1 4

  19. ITC-07 Paper 26.3 Results • Column 2: The number of gate delay faults - Both slow-to-rise & slow-to-fall transitions

  20. ITC-07 Paper 26.3 Results • Column 3: Fault coverage achieved – detection assumed irrespective of fault size. Equivalent to transition fault coverage.

  21. ITC-07 Paper 26.3 Results • Columns 4 & 5: Consider only detected faults that lie on paths with length at least 70% of the longest path; detectable delay fault size below 30% of critical path delay.

  22. ITC-07 Paper 26.3 Results • Columns 4 & 5: About ½ critical gate delay faults can be erroneously assumed to be detected if signal reconvergences are ignored.

  23. ITC-07 Paper 26.3 Conclusion • Conventional min-max delay simulation produces extra hazards because correlations between signals are neglected. • Future work: General analysis of reconvergent fanouts • How does this analysis affect static timing analysis? • Timing simulation? • Dynamic timing analysis?

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