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Instruction Set Architecture

Instruction Set Architecture

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Instruction Set Architecture

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  1. Announcements groups homework 1st day reading (2.6-2.10) 2nd day reading (1.4) ** Bring green sheets Instruction Set Architecture or “How to talk to computers if you aren’t in Star Trek” Peer Instruction Lecture Materials for Computer ArchitecturebyDr. Leo Porteris licensed under aCreative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.

  2. What is Computer Architecture? Computer Architecture = Machine Organization + Instruction Set Architecture What the machine looks like How you talk to the machine

  3. How to speak computer? lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) 1000110001100010000000000000000 1000110011110010000000000000100 1010110011110010000000000000000 1010110001100010000000000000100 1 2 temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; ALUOP[0:3] <= InstReg[9:11] & MASK 3 4

  4. How to Speak Computer Compiler lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) Assembly Language Program Assembler 1000110001100010000000000000000 1000110011110010000000000000100 1010110011110010000000000000000 1010110001100010000000000000100 Machine Language Program Machine Interpretation Control Signal Spec ALUOP[0:3] <= InstReg[9:11] & MASK High Level Language Program Discuss what classes cover these parts + what they will do in the lab

  5. The Instruction Set Architecture ° is the agreed-upon interface between all the software that runs on the machine and the hardware that executes it. Application Operating System Compiler Instruction Set Architecture Instr. Set Proc. I/O system Digital Design Circuit Design More in Chapter 2 Talk about impact of legacy code.

  6. The Instruction Set Architecture • that part of the architecture that is visible to the programmer • opcodes (available instructions) • number and types of registers • instruction formats • storage access, addressing modes • exceptional conditions You will make this in the lab!

  7. Which of the following statement is generally true about ISAs?

  8. Examples of ISAs • Intel 80x86/pentium • VAX • MIPS • SPARC • Alpha AXP • IBM 360 • Intel IA-64 (Itanium) • PowerPC • IBM Cell SPE Main point – many machines map to 1 ISA

  9. Computer Organization • Once you have decided on an ISA, you must decide how to design the hardware to execute those programs written in the ISA as fast as possible • (or as cheaply as possible, or using as little power as possible, …). • This must be done every time a new implementation of the architecture is released, with typically very different technological constraints.

  10. Key ISA decisions You’ve learned ISAs – now we’re focusing on DESIGNING ISAs • operations • how many? • which ones • operands • how many? • location • types • how to specify? • instruction format • size • how many formats? destination operand operation y = x + b source operands (add r1, r2, r5) how does the computer know what 0001 0100 1101 1111 means?

  11. Your architecture supports 16 instructions and 16 registers (0-15). You have fixed width instructions which are 16 bits. How many register operands can you specify (explicitly) in an add instruction? LAB!!! (Specify vs. have --- implicit) Just have them discuss for ~1 min.

  12. Your architecture supports 16 instructions and 32 registers (0-31). You have fixed width instructions which are 16 bits. How many register operands can you specify (explicitly) in an add instruction? LAB!!! Just have them discuss for ~1 min. Also point out impact of 32 instructions and MIPS funct trick

  13. Instruction Formats-what does each bit mean? • Having many different instruction formats... • complicates decoding • uses more instruction bits (to specify the format) VAX 11 instruction format Serial decoding

  14. MIPS Instruction Formats 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits opcode rs rd sa funct rt opcode rs rt immediate opcode target Would be really hard to have less than three Much more than three makes decoding more serial, again

  15. MIPS Instruction Formats 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits opcode rs rd sa funct rt opcode rs rt immediate opcode target

  16. Convert this MIPS machine instruction to assembly: 0010 0001 0001 0000 0000 0000 0010 0010 ISOMORPHIC A

  17. Convert this MIPS machine instruction to assembly: 1000 1101 0001 0000 0000 0000 0000 1000 ISOMORPHIC C

  18. Convert this MIPS machine instruction to assembly: 0000 0001 0001 0000 1111 1000 0010 0100 A is correct

  19. Accessing the Operands There are typically two locations for operands – registers (internal storage - $t0, $a0) and memory. In each column we have which - reg or mem - is better. Which row is correct? Explain each – but then point out how this leads to load/store

  20. can do: add r1=r2+r3 and load r3, M(address) forces heavy dependence on registers, which is exactly what you want in today’s CPUs can’t do add r1 = r2 + M(address) - more instructions + fast implementation (e.g., easy pipelining) Load-store architectures Which is it that we care about? Why else can’t do address? (hint – fixed instruction length)

  21. How Many Operands?Basic ISA Classes Accumulator: 1 address add A acc  acc + mem[A] Stack: 0 address add tos  tos + next General Purpose Register: 2 address add A B EA(A)  EA(A) + EA(B) 3 address add A B C EA(A)  EA(B) + EA(C) Load/Store: 3 address add Ra Rb Rc Ra  Rb + Rc load Ra Rb Ra  mem[Rb] store Ra Rb mem[Rb]  Ra Talk through each one – just describe what it is. Not in the text – but on the CD. Be sure to mention stacks often use internal registers

  22. A = BC+BY Push B pushY mult pushb pushC mult add popA Load B multY store temp Load B Mult C add temp store A R1=B*Y R2=B*C A=R1+R2 R1=B R2=C R3=Y R4=R1*R2 R5=R1*R3 R6=R4+R5 A=R6

  23. A = BC+XY ISOMORPHIC In an alternative universe, memory is VERY SLOW to access relative to registers (internal storage). Which ISA would you most likely find in this universe? A. Stack B. Accumulator C. Reg-Reg D. Accumulator and Reg-mem E. Stack and Accumulator Explain that these are sample codes – but the question is in general

  24. A = BC+XY • In an alternative universe – registers (internal storage) are very expensive, and memory is not as slow. Which ISA would you most likely find in this universe? • Stack • Accumulator • Reg-Reg • Reg-Mem and Stack • Both Reg-Reg and Reg-Mem

  25. Match the addressing mode with its example: I’m not a big fan of memorizing “terms” but these are used frequently enough that you need to know them.

  26. MIPS addressing modes give flexibility immediate add $1, $2, #35 base + displacement lw $1, disp($2) Get reg ind and absolute for free OP rs rt immediate rs rt immediate register indirect  disp/immediate = 0 absolute  (rs) = 0 (R1 = M[R2 + disp])

  27. Memory Organization • Viewed as a large, single-dimension array, with an address. • A memory address is an index into the array • “______________" means that the index points to a byte of memory. Byte addressing 0 8 bits of data 1 8 bits of data 2 8 bits of data 3 8 bits of data 4 8 bits of data 5 8 bits of data 6 8 bits of data ...

  28. Processor X is 16 bit byte-addressable. If you have a pointer at address 0000 0000 0000 1000 and you increment it by one (0000 0000 0000 1001). What does the new pointer (0000 0000 0000 1001) point to, relative to the original pointer (0000 0000 0000 1000)? ISOMORPHIC B is correct • The next word in memory • The next byte in memory • Either the next word or byte – depends on if you use that address for a load byte or load word • Pointers are a high level construct – they don’t make sense pointing to raw memory addresses. • None of the above.

  29. Processor Y is 14 bit word-addressable. If you have a pointer at address 00 0000 0000 1000 and you increment it by one (00 0000 0000 1001). What does the new pointer (00 0000 0000 1001) point to, relative to the original pointer (00 0000 0000 1000)? ISOMORPHIC A correct • The next word in memory • The next byte in memory • Either the next word or byte – depends on if you use that address for a load byte or load word • Pointers are a high level construct – they don’t make sense pointing to raw memory addresses. • None of the above.

  30. Reading Quiz Variant • You have the following code in C:for(int i = 0; i< 10;i++){A[i]=i;}Where A is an array of shorts (16 bit/half-word).Let's suppose that the base address of A is in $s0 and has the value of 1000 (base ten).What byte address(es) correspond to A[5]? Byte word addressing can be problematic to think about – the book Likes to jump around between them. I’ll try to be consistent in class.

  31. Memory Organization • Bytes are nice, but most data items use larger "words" • For MIPS, a word is 32 bits or 4 bytes. • 232 bytes with byte addresses from 0 to 2^32-1 • 230 words with byte addresses 0, 4, 8, ... 2^32-4 • Words are aligned i.e., what are the least 2 significant bits of a word address? 0 32 bits of data 4 32 bits of data Registers hold 32 bits of data 8 32 bits of data 12 32 bits of data

  32. MIPS Review All our processors will be mips based – so just wanna go over it.

  33. The MIPS ISA, so far • fixed 32-bit instructions • 3 instruction formats • 3-operand, load-store architecture • 32 general-purpose registers (integer, floating point) • R0 always equals 0. • 2 special-purpose integer registers, HI and LO, because multiply and divide produce more than 32 bits. • registers are 32-bits wide (word) • register, immediate, and base+displacement addressing modes

  34. What’s left • which instructions? • odds and ends

  35. Which instructions? • arithmetic • logical • data transfer • conditional branch • unconditional jump

  36. Which instructions (integer) • arithmetic • add, subtract, multiply, divide • logical • and, or, shift left, shift right • data transfer • load word, store word

  37. Control Flow • Jumps • Procedure call (jump subroutine) • Conditional Branch • Used to implement, for example, if-then-else logic, loops, etc. • A conditional branch must specify two things • Condition under which the branch is taken • Location that the branch jumps to if taken (target)

  38. What form of addressing is used by branch instructions? Mention C isn’t incorrect – and branches tend to be backward, but if they weren’t close – we couldn’t do relative

  39. High level code often has code like this: if(i<j) { i++; } Assume $t0 has i and $t1 has j. (slt rd, rs, rt does: R[rd]=1 if R[rs]<R[rt], else R[rd] = 0.) Which of the following is the correct translation of the above code to MIPS assembly (recall $zero is always 0): slt $t2, $t0, $t1 bne $t2, $zero, false addi $t0, $t0, 1 false: next instruction slt $t2, $t1, $t0 bne $t2, $zero, true true: addi $t0, $t0, 1 next instruction slt $t2, $t1, $t0 beq $t2, $zero, false addi $t0, $t0, 1 false: next instruction A B C slt $t2, $t0, $t1 beq $t2, $zero, false addi $t0, $t0, 1 false: next instruction Mention useless bne in B D is correct None of the above D E

  40. Jump instructions have a 26-bit immediate. Since an address must be word aligned we can always use 00 as the lowest bits. To make a 32 bit address, what are the top 4 bits?

  41. What is the most common use of a jal instruction and why? Mention jr

  42. To summarize:

  43. Review -- Instruction Execution in a CPU Memory2 Watch lw typo On cheat sheet CPU Registers10 Program Counter address10: R0 R1 R2 R3 R4 R5 ... 0 36 60000 45 198 12 ... 10001100010000110100111000100000 00000000011000010010100000100000 00000000000000000000000000111001 10000 10004 10000 Instruction Buffer 57 80000 op rs rt rd shamt immediate/disp • What happens when you execute the next instruction? • PC=10004 • R[R3] = 80000 • R[R3] = 57 • Both A and B • Both A and C in1 in2 addr ALU operation Load/Store Unit out data

  44. Review -- Instruction Execution in a CPU Memory2 CPU Registers10 Program Counter UPDATE! 10004 and R3=57 address10: R0 R1 R2 R3 R4 R5 ... 0 36 60000 45 198 12 ... 10001100010000110100111000100000 00000000011000010010100000100000 00000000000000000000000000111001 10000 10004 10000 Instruction Buffer 80000 op rs rt rd shamt immediate/disp • What happens when you execute the next instruction? • PC=10008 • R[R5] = 93 • R[R3] = 48 • Both A and B • Both A and C in1 in2 addr ALU operation Load/Store Unit out data

  45. Key Points • MIPS is a general-purpose register, load-store, fixed-instruction-length architecture. • MIPS is optimized for fast pipelined performance, not for low instruction count • Historic architectures favored code size over parallelism. • MIPS most complex addressing mode, for both branches and loads/stores is base + displacement.