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Digital I/O on the PIC32

Digital I/O on the PIC32. Heigh -Ho, Heigh -Ho, it’s off the chip we go!. Ports. Our device has seven ports, labeled A – G, each consisting of sixteen bits. The rightmost bit position is BIT_0.

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Digital I/O on the PIC32

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  1. Digital I/O on the PIC32 Heigh-Ho, Heigh-Ho,it’s off the chip we go!

  2. Ports • Our device has seven ports, labeled A – G, each consisting of sixteen bits. The rightmost bit position is BIT_0. • Each port is controlled by three special function registers (SFRs): TRISx, ODCx, and LATx, e.g., TRISA for port A. • Each bit of a port can be individually controlled. • The SFRs are each 32-bits, but only the 16 LSB affect port bits.

  3. TRISx

  4. ODCx Registers

  5. PORTx versus LATx • A fourth SFR, PORTx, is used to access pins • Writing to PORTx loads the LATx register. Equivalent to writing to LATx • Reading from PORTx reads the synchronized logic value on the external pin • Reading from LATx reads the LATx contents, not the pin!!! • Advice: Read from PORTx, write to LATx

  6. PORTx and LATxContol

  7. PORTx and LATx

  8. Additional SFRs • Additional SFRs are defined to facilitate common port operations: CLR, SET, INV • Associated with each of the four SFRs, e.g., TRISxCLR, PORTxINV • Operation on a particular bit is enabled by a ‘1’ in the corresponding bit position of a mask • For example, LATBINV = 0x000C toggles bits 2 and 3 of Port B • Equivalent to LATBINV = (BIT_2 | BIT_3)

  9. SET, CLR, INV

  10. Read-Modify-Write versus Atomic

  11. FRM Table

  12. Peripheral Libraries • Under “Help” or in Peripheral Library Guide • Simplifies configuration • More readable and portable • Individual bits selected via a bit mask, e.g. PORTWrite(IOPORT_B, (BIT_2 | BIT_4);

  13. Help>Help Contents>XC32 Toolchain>XC32 Peripheral Libraries

  14. Where’s that Pin?!?! • A couple of ways to find the information. For example, button to LED. • Look at the Cerebot RM, p. 9 or 30 • Verify against Cerebot schematic, p. 5 • Verify against PIC32 DS, p. 15 or 38

  15. Cerebot RM

  16. Cerebot RM (cont)

  17. Cerebot Schematic

  18. Noise Margins, Drive and Load • Output voltage requirements (under load) • Input voltage requirements • Noise margin is the difference between the “worst” output voltage and the “worst” input voltage • Input leakage current • Absolute maximums (!!!)

  19. Noise Margins

  20. Output Specifications

  21. Input Specifications

  22. Noise Margin Calculation • NMH = Voh_min – Vih_min = 2.4 – 0.65*3.3 = 255 mV with -10 mA load • NML = Vil_max - Vol_max = 0.2*3.3 – 0.4 = 260 mV with 10 mA load

  23. Input Leakage

  24. Absolute Maximums

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