Process Variation Aware Clock Tree Routing

1. Process Variation Aware Clock Tree Routing Bing Lu Cadence Jiang Hu Texas A&M Univ Gary Ellis IBM Corp Haihua Su IBM Corp ISPD'03

2. Outline • Introduction • Previous work • Problem formulation • Minimum skew violation clock tree • Experimental results • Extension to bounded skew clock tree • Conclusion ISPD'03

3. Spot defects Mask misalignment Process Variation Etching errors Gate length tox Junction depth T W S H Gate width Ground plane ISPD'03

4. Impact to Clock Skew • 20-30% variation on clock skew, mostly due to clock buffers ( Zanella, et al., TCAD 12/2000 ) • Interconnect variations may cause up to 25% variation on clock skew ( Y. Liu, et al., DAC 2000 ) • Undesired skew  bottleneck of clock frequency ISPD'03

5. Outline • Introduction • Previous work • Problem formulation • Minimum skew violation clock tree • Experimental results • Extension to bounded skew clock tree • Conclusion ISPD'03

6. Previous Work • Buffer insertion/sizing [Chung and Cheng, ICCAD 94] [Xi and Dai, DAC 95] • Wire sizing [Pullela, Menezes and Pillage, DAC 93] • Non-tree topology [Lin and Wong, ICCAD 94] [Su and Sapatneker, ICCAD 01] • Abstract topology [Velenis, Friedman and Papaefthymiou, ISCAS 01] ISPD'03

7. Focus on Clock Tree Routing • Interconnect variation is significantly important • Unlike transistors, worst case skew from interconnect variation is not at corner points • Result can be applied as a sub-network in buffered/non-tree clock network ISPD'03

8. Wl Wu Ws -3-2-1+1+2+3 68.26% 95.44% 99.74% Wire Width Variation Model • Wire width: w = Ws +  • Ws = W0 +  •x +  •y • Lower limit: Wl = Ws - 3 • Upper limit: Wu = Ws + 3 • : standarddeviation  =  = 3  dmax dmaxmax dist between sinks ISPD'03

9. Outline • Introduction • Previous work • Problem formulation • Minimum skew violation clock tree • Experimental results • Extension to bounded skew clock tree • Conclusion ISPD'03

10. Problem Formulation • Permissible range for sink siand sj [ LPRij, UPRij] • Skew violation max ( LPRij – skewij, skewij – UPRij ) • Minimizing Skew Violation ( MinSV ): Given a set of clock sinks { s1, s2, …, sn }, skew permissible ranges for all pairs of sinks, [Wl, Wu], find a clock routing tree such that the max skew violation among all sink pairs is minimized ISPD'03

11. Assumptions • Elmore delay model • Given abstract topology ISPD'03

12. Outline • Introduction • Previous work • Problem formulation • Minimum skew violation clock tree • Experimental results • Extension to bounded skew clock tree • Conclusion ISPD'03

13. DME Based Framework • Deferred Merge Embedding (DME) • Bottom-up, find merging segments • Top-down, find locations for internal nodes ISPD'03

14. Dij z ni nj n si sj Find Merging Locations • For particular z value • Skew range [ skew ij, min, skew ij, max ] • z , range shifts to greater values • z , range shifts to smaller values • Adjust z such that center of skew range is aligned to center of permissible range • In DME, adjust z such that skew ij = 0 ISPD'03

15. Dij Skew range z = 0 Skew range z = Dij z ni nj n si sj Permissible range Align Skew Range ISPD'03

16. Skew range z = 0 Skew range z = 0 Skew range z = Dij Skew range z = Dij Permissible range Permissible range When Snaking Necessary Dij Dij n n nj ni nj ni si sj si sj ISPD'03

17. Worst Case Skew Estimation • skew ij,min = t i,min – t j,max • skew ij,max = t i,max – t j,min • Need to estimate min and max delay to a sink under process variation ISPD'03

18. l w C Worst Case Delay Estimation: Single Sink • Wire capacitance clw • Wire resistance rl/w • t = rcl2/2 + rl C/w • tmin = rcl2/2 + rl C/WU • tmax = rcl2/2 + rl C/WL ISPD'03

19. Worst Case Delay Estimation: Multiple Sinks • t pi,min • Width of path np -> si is WU • Width of wires not on np->siis WL • t pi,max • Width of path np -> si is WL • Width of wires not on np->siis WU sk np si sj ISPD'03

20. How to Choose Sink Pair • How to choose si in left subtree and sj in right subtree? • Ideally, need to evaluate all sink pairs between left and right subtree • Greatly increase computation cost • Heuristic: pick the most critical pair Criticalityij = dij dmax+ PRmin  PRij dmax: max sink pair distance PRmin: min permissible range ni nj n si sj ISPD'03

21. Outline • Introduction • Previous work • Problem formulation • Minimum skew violation clock tree • Experimental results • Extension to bounded skew clock tree • Conclusion ISPD'03

22. Experiments • Benchmark circuits r1-r5 • SUN Blade-100 workstation, 512M memory • Compare with extended DME • Align nominal skew to center of permissible range • S: permissible range LPR, UPR symmetric wrt 0 • NS: LPR, UPR asymmetric wrt 0 ISPD'03

23. Number of Skew Violations ISPD'03

24. Maximum Skew Violation ISPD'03

25. Outline • Introduction • Previous work • Problem formulation • Minimum skew violation clock tree • Experimental results • Extension to bounded skew clock tree • Conclusion ISPD'03

26. Pair-wise Bounded Skew Routing • Minimizing Wirelength s.t. Skew Constraints: Given a set of clock sinks { s1, s2, …, sn }, skew permissible ranges for all pairs of sinks, find a clock routing tree such that the total wirelength is minimized while all permissible range are satisfied • Find merging regions instead of merging segments • Similar to Bounded Skew Clock Routing [Cong, et al., ACM TODAES 98] • Pair-wise skew permissible range vs. global skew bound • More wirelength reduction ISPD'03

27. Outline • Introduction • Previous work • Problem formulation • Minimum skew violation clock tree • Experimental results • Extension to bounded skew clock tree • Conclusion ISPD'03

28. Conclusion • Wire width variation needs to be considered in clock tree routing • Worst delay variation can be estimated given the wire width variation range • Our MinSV method significantly improves tolerance to wire width variation • Our method can be extended to pair-wise bounded skew routing to further reduce the total wire length ISPD'03

29. Thank you! ISPD'03