Multi-Split-Row Threshold Decoding Implementations for LDPC Codes

1. Multi-Split-Row Threshold Decoding Implementations for LDPC Codes Tinoosh Mohsenin, Dean Truong and Bevan M. Baas VLSI Computation Lab, ECE Department University of California, Davis

2. Outline • Introduction LDPC Decoding • Goals and Key Features • Split-Row Threshold Decoding Method • Multi-Split-Row Threshold Decoder Implementations and Results • Conclusion

3. LDPC Decoding • Message passing decoding • LDPC decoding challenges • High interconnect complexity for large number of processing nodes • Large delay, area, and power dissipation caused by long and global wire

4. Outline • Introduction to LDPC Decoding • Goals and Key Features • Split-Row Threshold Decoding Method • Multi-Split-Row Threshold Decoder Implementations and Results • Conclusion

5. LDPC Decoder Design Goals and Features • Key goals • Very high throughput and high energy efficiency • Area efficient (small circuit area) • Well suited for long-length and large row weight LDPC codes • Easy implementation with automatic CAD tools • Good error performance • Split-Row decoding key features • Reduced interconnect complexity • Reduced processor complexity T. Mohsenin and B. Baas, “Split-row: A reduced complexity, high throughput LDPC decoder architecture,” in ICCD, 2006 T. Mohsenin and B. Baas, “High-throughput LDPC decoders using a multiple Split- Row method,” in ICASSP, 2007

6. 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 H = 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 H H split - sp 0 split - sp 1 C 1 C 1 sp 1 sp 0 V 10 V 8 V 3 V 5 Standard MinSum vs. Split-Row Decoding Standard MinSum decoding Split-Row decoding reduction of check processor area reduction of input wires to check processor

7. Problem with Original Split-Row Algorithm • 0.5 – 0.7 dB error performance loss from MinSum Normalized and SPA. • In original MinSum Split-Row each partition has no information of the minimum value of the other partition.

8. Outline • Introduction to LDPC Decoding • Goals and Key Features • Split-Row Threshold Decoding Method • Multi-Split-Row Threshold Decoder Implementation and results • Conclusion

9. MinSum Split-Row Threshold Algorithm • A signal (Threshold_en) is passed from each partition, which indicates whether a partition has a minimum less than a given threshold (T). • Check nodes now take as their minimum of their own local Min or T. • Optimum threshold value (T) is obtained by empirical simulations Threshold_en Sp1=1 Threshold_en Sp0=0 Mohsenin et al, "An Improved Split-Row Thresholding Decoding Algorithm for LDPC Codes,"To appear to IEEE International Conference on Communications (ICC'09).

10. 32/Spn variable nodes (2048,1723) (6,32) 10GBASE-T code • Code length =2048 • Information length=1723 • Row size (No. of parity checks)=384 • Row weight (Wr)=32 • Column weight (Wc)=6

11. Error Performance for (2048,1723) 10GBASE-T Code • MS Split-Row-16 Threshold is 0.22 dB away from MS and is 0.12 dB better than Split-Row-2 Original. • Threshold (T)=0.2 • In the Plot: • BPSK modulation • AWGN channel • Maximum 15 iterations • Based on 80 error blocks 0.22 dB 0.12 dB

12. Outline • Introduction to LDPC Decoding • Goals and Key Features • Split-Row Threshold Decoding Method • Multi-Split-Row Threshold Decoder Implementations and results • Conclusion

13. Delay Analysis for Decoders • Path1: propagation of Threshold_en passing through Spn-2 partitions • Path2: delay path through check and variable procs • For small Spn the interconnect delay is dominant because of wire interconnect complexity • As the number of partitioning increases Path 1 delay increases

14. Area Analysis for Decoders • In MinSum, the synthesis area deviates significantly from layout area due to low utilization. • Area break down per sub-block for MinSum and Split-16 • 75% of MinSum decoder is empty space for wiring 10% 38% Check Proc 11% 4% 75% Var Proc 43% Clk tree+ Regs 2% Wire (empty space) 17% Split-16 Threshold MinSum

15. Comparison of Decoders (6,32) (2048,1723) 10GBASE-T code with 15 decoding iterations.

16. Conclusion • Split-Row Threshold algorithm improves the error performance when compared with original Split-Row. • Split-Row Threshold allows for high level of partitionings without losing significant error performance. • Higher level of partitioning reduces the number of connections between check and variable processors. This results in a higher logic utilization and a smaller circuit. • We can meet the demands of high speed applications while obtaining very low area when compared to standard decoding.

17. Acknowledgements • Support • ST Microelectronics • NSF Grant 430090 and CAREER award 546907 • Intel • SRC GRC Grant 1598 and CSR Grant 1659 • Intellasys • UC Micro • SEM • Special thanks • Professor Shu Lin