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Semi-Parallel Reconfigurable Architecture for Real-time LDPC decoding

This paper presents a novel semi-parallel reconfigurable architecture designed for real-time Low-Density Parity-Check (LDPC) decoding. It compares various algorithms, examines the optimal scaling factor for performance enhancement, and introduces Bit Function Units (BFUs) and Check Function Units (CFUs) for efficient processing. The architecture implements quantization techniques and demonstrates superior throughput with a maximum data rate of 127 Mbps for a block length of 1536 bits. The study concludes with insights on overflow management and reduced interconnection complexity for enhanced decoder efficiency.

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Semi-Parallel Reconfigurable Architecture for Real-time LDPC decoding

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  1. Semi-Parallel Reconfigurable Architecture for Real-time LDPC decoding Karkooti, M.; Cavallaro, J.R.;Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004. International Conference on ,Volume: 1 ,April 5-7, 2004 Pages:579 - 585

  2. Outline • Introduction • Algorithms Comparison • Scaling factor • BFU (Bit function unit) • CFU (Check function unit) • Quantization • Conclusion

  3. Introduction • (3,6) LDPC codes • Min-sum algorithm • Parity check matrix is generated by shifting

  4. Algorithms Comparison

  5. Comparison • N is codeword length • K is message bits • Wc is column weight • Wr is row weight • b is the number of the bits per message • S is the folding factor

  6. Modified (Scaling) • Scaling factor of 0.8 is optimal for (3,6) LDPC code. • Scaling the soft info. not only compensates for loss of performance, but also results in superior performance.

  7. Architecture • Channel value are stored in MEMInitn • Iteration result are stored in MEMCodemn • Message are stored in MEMmn

  8. BFU • Scaling Factor: 0.5+0.25=0.75~=0.8 • Can be modified for irregular LDPC code

  9. BFU to Memories • S/M: split and merge unit • ADGB: Address generator for BFU

  10. CFU • Outi =min{abs(ini’)|i’!=i} • Min: Output will be minimum input • SM->2’s:Sign-magnitude to 2’s complement presentation

  11. CFU to Memories • S/M: split and merge unit. • ADGC: Address generator for CFU

  12. Quantization • Sign + integral + fraction=1+2+2= 5 bits

  13. Cost

  14. Throughput • N=1536 K=768, S=16, μ=20 1536/16=96BFUs 768/16=48CFUs • For a LDPC code with the block length of 1536 bits, the decoder achieves a data rate of up to 127Mbps.

  15. Conclusion • Overflow issue  Scaling factor & LLR • Simultaneously multiple access  Pack message • Reduce interconnection complexity  Partition parity check matrix

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