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Brief Introduction to Verilog

Brief Introduction to Verilog. Weiping Shi. What is Verilog?. It is a hardware description language Originally designed to model and verify a design Later became an efficient design entry method Allows designers to quickly create and debug large scale designs Similar to C in syntax

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Brief Introduction to Verilog

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  1. Brief Introduction to Verilog Weiping Shi

  2. What is Verilog? • It is a hardware description language • Originally designed to model and verify a design • Later became an efficient design entry method • Allows designers to quickly create and debug large scale designs • Similar to C in syntax • Verilog will be used in later labs

  3. a sum b c_out_bar c_out Sample Half Adder module Add_half (sum, c_out, a, b); input a, b; output sum, c_out; wire c_out_bar; xor (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule

  4. Module Hierarchy • Modules can be instantiated within other modules • Allows for simplicity and regularity in the design • Example: Use two half adders to create a full adder

  5. Module Hierarchy Example module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; wire c_out_bar; xor (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule Module Add_full ( sum, c_out, a, b, c_in ); // parent module input a, b, c_in; output c_out, sum; wire w1, w2, w3; Add_half M1 ( w1, w2, a, b ); Add_half M2 ( sum, w3, w1, c_in ); // child module or ( c_out, w2, w3 ); // primitive instantiation endmodule

  6. Alternative Half Adders module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; assign { c_out, sum } = a + b; // Continuous assignment endmodule module Add_half (sum, c_out, a, b ); input a, b; output sum, c_out; reg sum, c_out; always @ ( a or b) // behavior description begin sum = a ^ b; c_out = a & b; end endmodule

  7. Structural v.s. Behavioral • Verilog can be structural or behavioral • Structural definition specifies the gates and their connections explicitly • Behavioral definition specifies the functionality of a design • Does not contain any structural information such as transistors or gates • Logic synthesis software implements the structural

  8. Behavioral Example2 Bit Comparator module comparator (a_greater, b_greater, equal, a, b); input a, b; output a_greater, b_greater, equal; reg a_greater, b_greater, equal; always @(a or b) // either a or b changes begin if (a > b) begin a_greater = 1; b_greater = 0; equal = 0; end if (a<b) begin a_greater = 0; b_greater = 1; equal = 0; end if (a==b) begin a_greater = 0; b_greater = 0; equal = 1; end end endmodule

  9. Alternate comparator module comparator (a_greater, b_greater, equal, a, b); input a, b; output a_greater, b_greater, equal; assign a_greater = (a > b) ? 1 : 0; assign b_greater = (a < b) ? 1 : 0; assign equal = (a==b) ? 1 : 0; endmodule Uses a conditional continuous assignment to set the outputs.

  10. Clarification • Registers are used when an output is updated on an event. The value must be held until a new event updates that value. • Assign statements are used when the output is continuously being assigned.

  11. Testbench • Manipulate the module inputs to observe the circuit reaction • Uses module hierarchy • Introduces the concept of delay

  12. Sample Testbench for a Half Adder module tbench; reg a,b; // regs connect to module inputs wire sum,cout; // wires connect to module outputs half_adder M1(cout,sum,a,b); // instantiate the half adder initial begin a = 0, b = 0; //time 0 #5 a = 1, b = 0; //time 5 #3 a = 1, b = 1; //time 8 #4 a = 0, b = 1; //time 12 #52 a = 0, b = 0; //time 64 #70 $finish; //stops the simulation end initial begin $monitor($time,”a = %b, b=%b cout=%b sum=%b”,a,b,cout,sum);//displays the variable values at each //unit of time that an event occurs end endmodule

  13. Testbench Results Compiling source file "ha.v" Compiling source file "tbench.v" Highest level modules: tbench 0a = 0, b=0 cout=0 sum=0 5a = 1, b=0 cout=0 sum=1 8a = 1, b=1 cout=1 sum=0 12a = 0, b=1 cout=0 sum=1 64a = 0, b=0 cout=0 sum=0 "tbench.v": $finish at simulation time 134

  14. a = 1, b = 0 a: accelerator b: brake low stopped b = 1 b = 1 b = 1 a = 1, b = 0 b = 1 medium high a = 1, b = 0 a = 1, b = 0 FSM Example: Car accelerator brake speed clock

  15. Behavioral Description module car(speed, a, b, clock); input a, b, clock; output [1:0] speed; reg [1:0] speed; parameter stopped = 2’b00; parameter fast = 2’b11; always @(posedge clock or b) begin if (b == 1 && speed != stopped) speed = speed – 1; else if (b == 0 && a == 1 && speed != fast) speed = speed + 1; end endmodule

  16. Where to Get Verilog • CD in the back of the book, if you have Verilog version • Icarus Verilog • http://www.icarus.com/eda/verilog/

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