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R&D FOR TPC MPD/NICA READOUT ELECTRONICS PowerPoint Presentation
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R&D FOR TPC MPD/NICA READOUT ELECTRONICS

R&D FOR TPC MPD/NICA READOUT ELECTRONICS

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R&D FOR TPC MPD/NICA READOUT ELECTRONICS

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  1. R&D FOR TPC MPD/NICA READOUT ELECTRONICS S.Vereschagin, Yu.Zanevsky, F.Levchanovskiy S.Chernenko, G.Cheremukhina, S.Zaporozhets, A.Averyanov Laboratory of High Energy Physics, JINR, Dubna, Russia Varna, 2013

  2. CONTENS • Introduction (general characteristics of TPC/MPD, & readout electronics requirements) • FEE prototype (FEC-64) • Main option FEE (FEC-128 & RCU) • Conclusions

  3. General view of the MPD detector

  4. TPC/MPD ~110000 readout channels beam E 12 Readout chambers beam HV-electrode ~28 KV Field cage

  5. Main parameters of the TPC • Size: 3.4m(length) x 2.8m (diameter); • Drift gas: 90% Ar+10% Methane CH4 or 90%Ar+10% CO2; • Drift velocity: 5.5 cm/us(Ar + CH4), 2.3 cm/us (Ar + CO2); • Length of drift volume: 1.7 m; • Data readout: 2x12 sectors (MWPC, cathode pad readout); • Maximal event rate 5 kHz; • Total number of pads ~ 110000;

  6. Simulation results Central collision on TPC/MPD @ 9GeV

  7. Main parameters of the FEE TPC • Total number of channels ~ 110000 • Data stream from whole TPC – 5 GB/s • Low power consumption – less then 100 mW/ch • Fast optical transfer interface • Based on ASIC and FPGA

  8. Front-End Electronics prototype FEC-64 channels • Signal to noise ratio, S/N - 30 • NOISE < 1000e-(С=10-20 pF) • Dynamic Range - 1000 • Zero suppression • Buffer (4 / 8 events) PASA chip 16 channels ASIC (low noise amplification of the signal) FPGA - board control ALTRO chip 16 channels ASIC (digitization and signal processing) FTDI USB2.0 (prototype only)

  9. Processing in PASA & ALTRO - FWHM – 190ns - Baseline restoration after 1ms: ~ 5 % in amplifier / shaper ~ 0.1% in dig. chip FWHM ~ 190ns PASA ALTRO - Baseline corrections - Tail cancellation

  10. FEE TESTING FEE on the TPC prototype Pulse after amplification

  11. FEC-64 testing software

  12. Block diagram of FEE base 128 ch. Pad Plane ~4500 ch. DAQ PC FEC 1 Switch 1 Group 1 RCU FEC 8 Trigger FEC 1 Switch 8 Slow control FEC 8 Group 8

  13. FEE of RoC general diagram Trigger System Slow Control system DAQ PC 5 Gb/s Optical interface Ethernet HLT TPC RCU FEC group FEC group Switch Switch FEC group FEC group Switch Switch FEC group Switch

  14. TPC/MPD READOUT OUTLINE • Support high data throughput & maximum parallelization; • HLT(TPC), online reconstruction & events compression; • Use GPU NVIDIA for computing trigger decision; • Like ALICE, ATLAS & CBM experiments;

  15. DATA READOUT HLTdecision to MPD central trigger processor HLT Online reconstruction HLT TPC Permanent Data Storage Event builder PC 1 PC 24 From other detectors

  16. Maximum parallelization HLT - TPC ROC 1 TPC PCI-E 8 Gb/s and more GPU BOARD MB-PC FEE PCI-E 1x FEE PCI-E 1x ROC 24 TPC FEE PCI-E 1x

  17. Conclusions: • Prototype card has been designed • 6 prototype cards has been produced & tasted • Testing software was developed (LabView & C++) • Base FEE concept was developed • FEE design toward final version ongoing

  18. I would like to express our gratitude for the help to Victor Chepurnov(JINR) StepanRazin (JINR) Alexander Moskovsky (JINR) Luciano Musa (CERN)

  19. Thank you for your attention!

  20. Final version of FEE

  21. Basic version of FEC

  22. Switch node

  23. Readout Control Unit

  24. Choice of FPGA technology • SRAM, where the programmable switch is controlled by an SRAM memory cell. • Flash (or EPROM/EEPROM), where the switch is a floating gate transistor that can be turned off by injecting charge onto the floating gate. • Antifuse, where an electrically programmable switch forms a low resistance path between two metal layers.