EE 445S Real-Time Digital Signal Processing Lab Fall 2013

1. EE 445S Real-Time Digital Signal Processing LabFall 2013 Lab #2Generating a Sine Wave Using the Hardware & Software Tools for the TI TMS320C6748 DSP (Continued)Debarati Kundu (with the help of Mr. Eric Wilbur, TI)

2. EDMA • Idea is that, with EDMA, CPU can initiate data transfer and do other operations while transfer is in progress. • More efficient than using regular I/O which keeps CPU occupied during entire transfer. • EDMA controller: • Handles all data transfers between L2 cache and peripherals. • Can move data to and from any addressable memory spaces (internal memory, external memory and peripherals) independently of CPU operations.

3. EDMA Features • Has 64 channels that can be assigned priorities. • EDMA3 needs: • Source Address • Destination Address • Size of transfer • After an element transfer, addresses at source/destination can stay the same, get incremented or decremented. • Data transfers can be initiated by CPU or events (such as the McASP FIFO buffers full). • Programmable Transfer Burst Size: Transfers can be 8-bit bytes, 16-bit half-words, or 32-bit words. • Can transfer 2-dimensional data blocks.

4. EDMA Features • When an event occurs its transfer parameters are read from the Parameters RAM (PaRAM) and then sent to the address generation hardware. • After a programmed transfer, EDMA can continue transfers by linking to another transfer programmed in the PaRAM for same channel, or chaining to a transfer for another channel • Can generate transfer completion interrupts to the CPU along with a transfer complete code, for it to take desired action based on that code. • EDMA has a Quick DMA mode (QDMA) for quick, one-time transfers.

5. ACNT Bytes Frame 1 Array1 Array2 Array BCNT Frame 2 CCNT Frames Array1 Array2 Array BCNT Frame CCNT Array1 Array2 Array BCNT BCNT Arrays EDMA3 Terminology • 3-dimensional transfer consisting of ACNT, BCNT and CCNT: • ACNT = Array = # of contiguous ACNT bytes (16-bit unsigned, 0-65535) • BCNT = Frame = # of ACNT arrays (16-bit unsigned, 0-65535) • CCNT = Block = # of BCNT frames (16-bit unsigned, 0-65535) • Minimum transfer is an array of ACNT bytes • Total transfer count = ACNT * BCNT * CCNT

6. Example – How do you VIEW the transfer? • We need to transfer 12 bytes from “here” to “there”. Note: these are contiguous memory locations 8-bit • What is ACNT, BCNT and CCNT? • You can “view” the transfer several ways: ACNT = 1 BCNT = 4 CCNT = 3 ACNT = 2 BCNT = 2 CCNT = 3 ACNT = 12 BCNT = 1 CCNT = 1 • Which “view” is the best? Well, that depends on whatyour system needs and the type of synchronization…

7. Options 0 Source .. BCNT ACNT Destination 63 DSTBIDX SRCBIDX BCNTRLD LINK DSTCIDX SRCCIDX RSVD CCNT 31 0 EDMA Channel/Parameter RAM Sets • EDMA3 has 256 Parameter RAM sets (PSETs) that contain configuration information about a transfer • 64 DMA CHs and 4 QDMA CHs can be mapped to any one ofthe 256 PSETs and then triggered to run (by various methods) 64 DMA CHs PaRAM Set 0 PaRAM Set 1 .. PSET 63 4 QDMA CHs PSET 64 0 .. .. PSET 255 3 • Each PSET contains 12 registers: • Options (interrupt, chaining, sync mode, etc) • SRC/DST addresses • ACNT/BCNT/CCNT (size of transfer) • 4 SRC/DST Indexes • BCNTRLD (BCNT reload for 3D xfrs) • LINK (pointer to another PSET) Note: PSETs are dedicated EDMA RAM (not part of IRAM)

8. EDMA PaRAM: • The OPT field: • Sets the priority, • Sets the element size: 8, 16, or 32 bits, • Defines sources as 1, 2 or 3 -dimensional, • Enables/disables transfer complete interrupt, • Defines transfer complete code, • Sets source/destination address update modes.

9. “A” – Synchronization • An event (like the McBSP receive register full), triggersthe transfer of exactly 1 array of ACNT bytes (2 bytes) • Example: McBSP tied to a codec (you want to sync each transfer of a 16-bit word to the receive buffer being full or the transmit buffer being empty). EVTx EVTx EVTx Frame 1 Array1 Array2 Array BCNT Frame 2 Array1 Array2 Array BCNT Frame CCNT Array1 Array2 Array BCNT

10. “AB” – Synchronization • An event triggers a two-dimensional transfer of BCNT arraysof ACNT bytes (A*B) • Example: Line of video pixels (each line has BCNT pixels consisting of 3 bytes each – Y, Cb, Cr) EVTx Frame 1 Array1 Array2 Array BCNT Frame 2 Array1 Array2 Array BCNT Frame CCNT Array1 Array2 Array BCNT

11. EDMA • Event Processing Registers: • Event Register (ER): when event n occurs, bit n of ER is set. • Event Enable Register (EER): setting bit n of EER enables processing of that event. • Event Clear Register (ECR): setting a bit in ECR clears corresponding bit in ER, used by CPU to clear event flags. • Event Set Register (ESR): setting a bit in ESR sets corresponding bit in ER, used by CPU to submit event requests and for debugging.

12. Generate EDMA Interrupt (Setting IERbit) EDMA Channels EDMA Interrupt Generation Channel # Options TCC IPR IER 0 0 TCINTEN=0 TCC=0 IER0 = 0 1 0 TCC=1 TCINTEN=0 IER1 = 0 EDMA3CC_GINT . . . 1 TCINTEN=1 TCC=14 IER14 = 1 63 0 TCINTEN=0 TCC=63 IER63 = 0 Options TCINTEN TCC IER – EDMA Interrupt Enable Register (NOT the CPU IER)IPR – EDMA Interrupt Pending Register (set by TCC) 20 17 12 Use EDMA3 Low-Level Driver (LLD) to program EDMA’s IER bits

13. Linking • Needed when we want to repeat the transfer • Linking two or more channels together allowsthe EDMA to auto-reload a new configurationwhen the current transfer is complete • Linking still requires a trigger to start the transfer (manual, chain, or event) • We can link as many PSETs as we like, limited only by the number of PSETs on a device.

14. Chaining • Needed When one transfer completes, trigger another transfer to run (for example, Ch0 completes, kicks off Ch1) • Chaining actually refers to both an action and an event – the completed ‘action’ from the 1st channel is the ‘event’ for the next channel • We can chain as many channels as we like, only limited by the channels on a device • Chaining does NOT reload current channel configuration– that can only be accomplished by linking. It simply triggers another channel to run.