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Hardware Acceleration of A Boolean Satisfiability Solver

Xander Chin Braiden Brousseau Bill Teng. Hardware Acceleration of A Boolean Satisfiability Solver. Motivation. SAT Solvers are core computational engine for major applications EDA: testing and verification, logic synthesis, technology mapping, …

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Hardware Acceleration of A Boolean Satisfiability Solver

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  1. Xander Chin BraidenBrousseau Bill Teng Hardware Acceleration of A Boolean SatisfiabilitySolver

  2. Motivation • SAT Solvers are core computational engine for major applications • EDA: testing and verification, logic synthesis, technology mapping, … • AI: knowledge base deduction, automatic theorem proving, … • Software SAT Solvers has improved a lot in the last ten years, but performance is saturating • Further speed it up through hardware acceleration!

  3. SAT in a Nutshell (a very tiny nutshell) • Given a boolean formula, find variable assignments such that the formula is true or prove that no satisfying assignment exists • Conjunctive Normal Form: e.g. φ(a,b,c) = (a+b)(a’+b+c) literal clause • NP – Complete • For n variables, there are 2n possible truth assignments to be checked

  4. Algorithmic Pruning 0 1 X1 X2 X3 X4 S U S S U U U U U U U S U U S S Resolve Conflict !

  5. Some Solver Techniques • Propagation • Literal watches – literal to clause mapping • Decision heuristics – which variable should be assigned next? • Pruning • Conflict analysis – which assignments will never work? • Non-chronological backtracking – undoing failed decisions quickly

  6. Flexibility of Software • Software can easily implement complex pruning techniques that would be extremely difficult in hardware • New pruning techniques are demonstrating only incremental gains • Some of the complex techniques must be omitted in hardware • We must still implement the core techniques

  7. Hardware Architecture • Parts of SAT are memory-bound • Random access data patterns to clauses • Hardware acceleration by streaming burst accesses to memory to maximize bandwidth and custom intermediate caching Pipeline Direction DDR Memory Bound Logic Memory Bound Logic Memory Bound Logic Custom Cache Custom Cache Custom Cache microBlaze Processor

  8. Conclusions • Trade-off between • High-level complex algorithms in software • Low-level algorithms in hardware • Critical to performance! • Novel new software algorithms could potentially outperform our hardware system • System flexibility with soft-processor • Core techniques not likely going away any time soon

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