1 / 16

Advanced Hardware/Software Optimization Techniques for Application Specific MCSoC

Advanced Hardware/Software Optimization Techniques for Application Specific MCSoC. m 5151117 Yumiko Kimezawa Supervised by Prof. Ben Abderazek. Outline. Background Research Motivation Research goal Proposal Conclusion Schedule. Background. Electrocardiography (ECG)

jihan
Télécharger la présentation

Advanced Hardware/Software Optimization Techniques for Application Specific MCSoC

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Master's Thesis Research Plan Advanced Hardware/Software Optimization Techniques for Application Specific MCSoC m5151117 Yumiko Kimezawa Supervised by Prof. Ben Abderazek

  2. Outline Master's Thesis Research Plan • Background • Research Motivation • Research goal • Proposal • Conclusion • Schedule

  3. Background Master's Thesis Research Plan • Electrocardiography (ECG) • For diagnosis of heart disease • ECG examination currently used • 12-lead ECG • The time required to put leads on the patient skin is only few minutes • It is impossible to diagnose whether the patient’s heart is normal or not • Holter monitors • Collecting ECG signals from the patient over a day • Taking too hours to analyze ECG signals

  4. Background (2) Master's Thesis Research Plan • New ECG processing system is necessary • 12-lead • Real time • small • Processing ECG signals involves heavy computation • Previous proposed ECG processing system • - Parallel processing using additional cores for analyzing ECG signals

  5. System architecture Master's Thesis Research Plan • 3-lead system is implemented • The total logic utilization is about 3 times as large as one of single-lead system • The total processing time is about 50 % from the single lead system External Memory Buffer ECG Signal Analysis ADC 1 FIR 1 Patient: A P = # mV Q = # mV R = # mV S = # mV T = # mV U = # mV Interval = # ms ADC 12 FIR 12 12 leads Not implemented 2:Filtering 3:Analysis 4:Display 1:Signal reading Out ideal system architecture

  6. System architecture (2) Master's Thesis Research Plan • The system consists of mainly 2 modules • Master module • Signal reading, filtering and display part • PPD module • Analyzing ECG signal using Period-Peaks Detection (PPD) algorithm

  7. Research motivation Master's Thesis Research Plan Problems • Input of current system is sample data already converted to digital • Impractical • Parallelization adding additional cores • The more leads, the larger logic utilization • Display of analysis results • Screen is too narrow to display a lot of results

  8. Research motivation Master's Thesis Research Plan Research goal • Getting input data from people actually • Proposal of more small system • Integration with the real-time tool • Transferring analysis results the real-time tool • Using USB or ethernet

  9. Proposal Master's Thesis Research Plan • Hardware/Software optimization • Hardware • Implementing A/D converters • DMA controller • Software • Review of algorithm for analyzing ECG signals • Parallelizing the code manually

  10. Proposal architecture Master's Thesis Research Plan • This slide is in preparation • I am investigating how to connect DMA controller to the system • I will finish this slide until next week

  11. Conclusion Master's Thesis Research Plan • Previous proposed system is not high performance • Logic utilization is large • Processing time is not good • Implementing A/D converters to the system • The system becomes practical • Review of software code is needed • - For parallelization

  12. Schedule Master's Thesis Research Plan • Master 1 • Implementing A/D converters • Until October • Adding DMA controller • Until November • Optimization of software • Until January

  13. Master's Thesis Research Plan

  14. System architecture Master's Thesis Research Plan : Data flow : Control signal Graphic LCD JTAG UART LED External Memory ECG Data Rom Slave CPU LED Controller Graphic LCD Controller Slave CPU Memory Avalon Bus Master CPU Timer Master CPU Memory FIR Filter Shared Memory Timer Master Module PPD Module

  15. Proposal architecture Master's Thesis Research Plan Data conversion HSMC DMA controller : Data flow : Control signal Graphic LCD JTAG UART FPGA LED Slave CPU Slave CPU Memory External Memory Graphic LCD Controller LED Controller A/D converter Avalon Bus Timer Master CPU Master CPU Memory FIR Filter Shared Memory Timer Master Module PPD Module Analog ECG data from people Line-in

  16. Background Master's Thesis Research Plan • ECG is used for diagnosis of heart disease • Haga’s system processes ECG signals one single lead at a time External Memory Buffer ECG Signal Analysis ADC 1 FIR 1 Patient: A P = # mV Q = # mV R = # mV S = # mV T = # mV U = # mV Interval = # ms ADC 12 FIR 12 12 leads 3:Analysis 2:Filtering 4:Display 1:Signal reading Figure: Haga’s system architecture proposed last year

More Related