INSTRUCTION SET PRINCIPLES

1. INSTRUCTION SET PRINCIPLES

2. Computer Architecture’s Changing Definition • 1950s to 1960s: Computer Architecture Course = Computer Arithmetic • 1970s to mid 1980s: Computer Architecture Course = Instruction Set Design, especially ISA appropriate for compilers • 1990s: Computer Architecture Course = Design of CPU, memory system, I/O system, Multiprocessors

3. Instruction Set Architecture (ISA) software instruction set hardware

4. Instruction Set Architecture • Instruction set architecture is the structure of a computer that a machine language programmer must understand to write a correct (timing independent) program for that machine. • The instruction set architecture is also the machine description that a hardware designer must understand to design a correct implementation of the computer.

5. Interface Design • A good interface: • Lasts through many implementations (portability, compatibility) • Is used in many different ways (generality) • Provides convenient functionality to higher levels • Permits an efficient implementation at lower levels use time imp 1 Interface use imp 2 use imp 3

6. Evolution of Instruction Sets Single Accumulator (EDSAC 1950) Accumulator + Index Registers (Manchester Mark I, IBM 700 series 1953) Separation of Programming Model from Implementation High-level Language Based Concept of a Family (B5000 1963) (IBM 360 1964) General Purpose Register Machines Complex Instruction Sets Load/Store Architecture (CDC 6600, Cray 1 1963-76) (Vax, Intel 432 1977-80) RISC (Mips,Sparc,HP-PA,IBM RS6000,PowerPC . . .1987) LIW/”EPIC”? (IA-64. . .1999)

7. Evolution of Instruction Sets • Major advances in computer architecture are typically associated with landmark instruction set designs • Ex: Stack vs GPR (System 360) • Design decisions must take into account: • technology • machine organization • programming languages • compiler technology • operating systems • And they in turn influence these

8. What Are the Components of an ISA? • Sometimes known as The Programmer’s Model of the machine • Storage cells • General and special purpose registers in the CPU • Many general purpose cells of same size in memory • Storage associated with I/O devices • The machine instruction set • The instruction set is the entire repertoire of machine operations • Makes use of storage cells, formats, and results of the fetch/execute cycle • i.e., register transfers

9. What Are the Components of an ISA? • The instruction format • Size and meaning of fields within the instruction • The nature of the fetch-execute cycle • Things that are done before the operation code is known

10. Computer Arithmetic Taxonomy of integers

11. Range of sign-and-magnitude integers # of Bits ---------- 8 16 32 Range ------------------------------------------------------- -127 -0 -32767 -0 -2,147,483,647-0 +0 +127 +0 +32767 +0 +2,147,483,647

12. Note: In sign-and-magnitude representation, the leftmost bit defines the sign of the number. If it is 0, the number is positive.If it is 1, the number is negative.

13. Example of storing sign-and-magnitude integers in two computers 8-bit allocation ------------ 00000111 11111100 overflow overflow 16-bit allocation ------------------------------ 0000000000000111 1000000001111100 0000000100000010 1110000010111000 Decimal------------ +7 -124 +258 -24,760

14. Example 8 Interpret 10111011 in decimal if the number was stored as a sign-and-magnitude integer. Solution Ignoring the leftmost bit, the remaining bits are 0111011. This number in decimal is 59. The leftmost bit is 1, so the number is –59.

15. Note: There are two 0s in one’s complement representation: positive and negative. In an 8-bit allocation: +0  00000000-0  11111111

16. Range of one’s complement integers # of Bits --------- 8 16 32 Range ------------------------------------------------------- -127 -0 -32767 -0 -2,147,483,647-0 +0 +127 +0 +32767 +0 +2,147,483,647

17. Note: In one’s complement representation, the leftmost bit defines the sign of the number. If it is 0, the number is positive.If it is 1, the number is negative.

18. Example of storing one’s complement integers in two different computers 8-bit allocation ------------ 00000111 11111000 01111100 10000011 overflow overflow 16-bit allocation ------------------------------ 0000000000000111 1111111111111000 0000000001111100 1111111110000011 0110000010111000 1001111101000111 Decimal------------ +7 -7 +124 -124 +24,760 -24,760

19. Note: One’s complement means reversing all bits. If you one’s complement a positive number, you get the corresponding negative number. If you one’s complement a negative number, you get the corresponding positive number. If you one’s complement a number twice, you get the original number.

20. Note: Two’s complement is the most common, the most important, and the most widely used representation of integers today.

21. Range of two’s complement integers # of Bits --------- 8 16 32 Range ------------------------------------------------------- -128 -32,768 -2,147,483,648 0 +127 0 +32,767 0 +2,147,483,647

22. Note: In two’s complement representation, the leftmost bit defines the sign of the number. If it is 0, the number is positive.If it is 1, the number is negative.

23. Example of storing two’s complement integers in two different computers 8-bit allocation ------------ 00000111 11111001 01111100 10000100 overflow overflow 16-bit allocation ------------------------------ 0000000000000111 1111111111111001 0000000001111100 1111111110000100 0110000010111000 1001111101001000 Decimal------------ +7 -7 +124 -124 +24,760 -24,760

24. Memory Addressing • How is a memory address interpreted? • Byte addressed: Provide access for bytes, half words, words, and double words (64 bits) • Conventions for ordering the bytes within a word: • Little Endian: put byte whose address xxxx00 at LSB position. Word address Data 0 3 2 1 0 4 7 6 5 4 • Big Endian: Put byte whose address xxxx00 at MSB position. Word address Data 0 0 1 2 3 4 4 5 6 7

25. Address Alignment • Access to objects larger than a byte must be aligned. • An access to an object of size S bytes at byte address A is aligned if A mod S =0. • Fig. 2.5 aligned and misaligned access Object Aligned at Misaligned at addressed byte offsets byte offsets ------------------------------------------------------------ Byte 0,1,2,3,4,5,6,7 Never Half word 0,2,4,6 1,3,5,7 Word 0,4 1,2,3,5,6,7, Double word 0 1,2,3,4,5,6,7 • A misaligned memory access will take multiple aligned memory references

26. Addressing Mode • How architectures specify the address of an object they will access? • In a GPR, an addressing mode can specify • a constant, • a register, • a location in memory (used to compute effective address). • Immediate or literals are usually considered as memory addressing mode. • Addressing modes that depend on the program counter is called PC-relative addressing. • Addressing modes can significantly reduce instruction counts, but may add to the complexity of building a machine and increase the average CPI.

27. Karnaugh map • The Karnaugh map, also known as the K-map, is a method to simplifyboolean algebra expressions. . • The Karnaugh map reduces the need for extensive calculations by taking advantage of humans' pattern-recognition capability. It also permits the rapid identification and elimination of potential race conditions.

28. Diagram showing K-map for f(A, B, C, D). 

29. Exercise • Consider the following expression, by using the K-Map method, create • 1- truth table • 2- draw K-Map • 3-Draw implicand • 4-Find equation