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기본개념. CPU. Memory. IO-1. IO-2. 2bytes. 2bytes. 8bytes. Address BUS Data BUS Control BUS. A3~A0 D7~D0. IO Map. Memory Map. 0 1 2 3. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15. IO-1 IO-2. A1~A0. A3~A0. Address Decoder. A1. 0. u nsigned char *port;
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기본개념 CPU Memory IO-1 IO-2 2bytes 2bytes 8bytes Address BUS Data BUS Control BUS A3~A0 D7~D0 IO Map Memory Map 0 1 2 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IO-1 IO-2 A1~A0 A3~A0
Address Decoder A1 0 unsigned char *port; port = (unsigned char *)0x0; *port = 0x12; 0 /IO1_CS 0 0 A1 /CS /IORQ 0 0 0 A0 A0 0 0 0 1 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 control 00010010 data 0 0 R/W R/W Control Register Write CPU IO-1
Address Decoder A1 0 unsigned char *port; unsigned char data; port = (unsigned char *)0x1; Data = *port; 0 /IO1_CS 0 0 A1 /CS /IORQ 0 1 1 A0 A0 1 0 1 0 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 control 00010010 data 10101111 1 1 R/W R/W Address Decoder 는 Logic Gate 로 구현 Nx2N Decoder 로 구현 PAL 이나 CPLD 로 구현 Data Register Read CPU IO-1
Control Register void port_init(void) { unsigned char *port; port =(unsigned char *) 0x03; *(port) = 0x90; // PA input, PB output, PC output } unsigned char getData_DIP(void) { unsigned char *port, data; port =(unsigned char *)0x00; data = *(port); return data; } main() { unsigned char DIP_data; port_init(); DIP_data = getData_DIP(); printf(“%0x”,DIP_data); // 10010111 이므로 97 출력 } 1 0 0 1 0 0 0 0 Mode 0 PA Input PB Output PC(low) Output PC(up) Output 입력장치 인터페이스 강의노트
Control Register void port_init(void) { unsigned char *port; port =(unsigned char *) 0x03; *(port) = 0x80; // PA input, PB output, PC output } void set_LED(unsigned char data) { unsigned char *port; port =(unsigned char *)0x00; *(port) = data; } main() { port_init(); set_LED(0x0F); } 1 0 0 0 0 0 0 0 Mode 0 PA Output PB Output PC(low) Output PC(up) Output 출력장치 인터페이스 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 강의노트
RS(address) Address (A0) R/W E 140nS D0-D7 Valid Data void clearscreen_lcd(void) { xdata unsigned char *pcode; // for External Memory pcode =(unsigned char xdata *)0xF000; *(pcode) = 0x00; // LCD_RS = 0; pcode = (unsigned char xdata *)0xF300; *(pcode) = CLEAR_DISPLAY; pcode = (unsigned char xdata *)0xF100; *(pcode) = 0x01; // LCD_EN = 1; *(pcode) = 0x00; // LCD_EN = 0; } void PutChar(unsigned char c) { pcode = (unsigned char xdata *)0xF000; *(pcode) = 0x01; // LCD_RS = 1; pcode = (unsigned char xdata *)0xF300; *(pcode) = c; pcode = (unsigned char xdata *)0xF100; *(pcode) = 0x01; // LCD_EN = 1; *(pcode) = 0x00; // LCD_EN = 0; } E RS R/W 8051 D0 D1 D2 D3 D4 D5 D6 D7 Character LCD LCD_EN LCD_RS LCD_RW P0[7:0], P2[7:0], ALE, /WR, /RD AD[7:0], A[15:8], ALE, /WR, /RD PORTA[7:0] CPLD 실습보드 CPLD Logic (Verilog HDL)