Pattern Sensitive Placement For Manufacturability

1. Pattern Sensitive Placement For Manufacturability Shiyan Hu, Jiang Hu Department of Electrical and Computer Engineering Texas A&M University College Station, TX, 77843

2. Outline • Lithography system • Motivation • Problem formulation • Algorithms • Experimental results • Conclusion

3. Lithography Process optical Part of layout mask oxidation photoresist photoresist coating removal (ashing) stepper exposure Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process spin, rinse, dry step

4. 193nm wavelength 45nm features Lithography System Illumination Source Mask Objective Lens Wafer

5. Motivation • Printability problem • Lithography technology: 193nm wavelength • VLSI technology: 45nm features • Lithography induced variations • Impact on timing and power • Even for 180nm technology, variations up to 20x in leakage power and 30% in frequency were reported.

6. 28nm, tolerable distortion: 2nm 193nm Lithography Tech. v.s. VLSI Tech.

7. Improve Printability by RET • Resolution Enhancement Technique (RET) • Post Physical Layout Design • Weakness: • Limited capacity and increasingly difficult • Expensive mask cost OPC

8. Design For Manufacturability (DFM) • Efforts are needed in all design and process stages. • Physical design considering printability: Design For Manufacturability (DFM). • To make RET easier and cheaper to apply

9. (From DAC’05) Previous Works on DFM • Regular fabric: • Introduce regular geometry, similar to FPGA • Compromised performance • Restricted design rules: • Not able to accurately capture lithography effects • Rule explosion: 2000 pages in 22nm technology

10. Previous Works on DFM Regular fabric: Introduce regular geometry, similar to FPGA Compromised performance • Restricted design rules: • Not able to accurately capture lithography effects • Rule explosion: 2000 pages in 22nm technology • RET-friendly detailed placement (ASPDAC’05): • Small spacing perturbation • No cell flipping, no cell relocation

11. Placement Our Problem • Physical layout design considering manufacturability • Cell Placement • Given a circuit, decide the physical location of each gate • A major step in the physical layout design flow • Objectives: small wirelength, small area, good timing, etc.

12. This Work • Post-placement optimization for printability • Post-placement optimization • Applicable to any existing placement to make it easier to print • Limit modification to retain benefits • Improve printability • Measurement of printability • How? • Relocation and Flipping

13. : EPE Measurement of Printability • Manufacturability cost • Edge Placement Error (EPE), Image Log Slope (ILS), process window,… From http://www.vlsitechnology.org/

14. Existing Placer Our Optimization Relocation and Flipping Hard to print by simulation Easy to print by simulation

15. 50% reduction in gate length deviation Cell Flipping to Improve Printability From http://www.vlsitechnology.org/

16. Pattern: part between horizontally adjacent cell pair Our Approach • Offline: • For each possible pattern formed by two cells, assign a manufacturability cost • Accurate lithography simulations • Results saved in a lookup table • Online: • Prefer easy-to-print patterns in design From http://www.vlsitechnology.org/

17. Problem Formulation • Given a cell placement • Perform post-processing optimizations, which can be cell flipping and relocation • Total manufacturability cost (sum of manufacturability cost over all patterns) is reduced subject to the modification (wire length) constraint.

18. Optimization Considering Cell Flipping • The algorithm is for row-based layout. • Perform optimization row by row. • For each row of cells, perform the dynamic programming style optimization.

19. Optimizing A Row by Cell Flipping 1 After processing the last cell, pick the solution with best manufacturability cost while satisfying wirelength constraint 2

20. Solution Characterization and Update • Each candidate solution is associated with • c: a cell • CE: cumulative manufacturability cost • CW: cumulative wire length • c is being processed, • CE  CE + manufacturability cost of new pattern • CW  HPWL on all nets not spanning on any unprocessed cell. c

21. Solution Pruning • Two candidate solutions • Solution 1: (c, CE1, CW1) • Solution 2: (c, CE2, CW2) • Solution 1 is inferior if • CE1 > CE2 : larger cumulative manufacturability cost • and CW1 > CW2 : larger cumulative wirelength • Whenever a solution becomes inferior, it is pruned.

22. Single Row Optimization • Allow both cell flipping and cell relocation. • Partition a row of cells into groups. • Small modification  a cell movable only within a group.

23. Pick groups for optimization Perform group optimization tentatively Accept the result if printability is improved and overhead satisfies constraint Flow for Single Row Optimization Partition a row of cells into groups Difficult

24. Difficult Difficult Group Optimization Compute the placement with best manufacturability cost (no wirelength constraint) Compute the placement with best wirelength (initial placement) Tradeoff: gradually tune best manufacturability placement towards the best wirelength placement

25. Placement with Best Manufacturability Cost : 0 : manufacturability cost 25

26. Placement with Best Manufacturability Cost : 0 : manufacturability cost

27. Placement with Best Manufacturability Cost : 0 : manufacturability cost

28. Placement with Best Manufacturability Cost Flipped : 0 : manufacturability cost 28

29. Placement with Best Manufacturability Cost : 0 : manufacturability cost 29

30. Placement with Best Manufacturability Cost : 0 : manufacturability cost Every placement corresponds to a Hamiltonian path

31. Minimum Cost Hamiltonian Path Problem • The placement with best manufacturability cost  the minimum cost Hamiltonian Path • No wirelength constraint • Well-known NP-hard problem • Closest point heuristic is used

32. Handle Wirelength Constraint • Start from best manufacturability solution • Gradually adjust it to satisfy wirelength constraint Best Manufacturability A B C D E Best Wire B A E D C • Reduce crossings: fewer crossings  closer to best wire solution  possible to satisfy the wirelength constraint

33. Handle Wirelength Constraint • Start from best manufacturability solution • Gradually adjust it to satisfy wirelength constraint Best Manufacturability A B C D E Best Wire B A E D C

34. Handle Wirelength Constraint • Start from best manufacturability solution • Gradually adjust it to satisfy wirelength constraint A B E D C Best Wire B A E D C • Able to get the solution with good manufacturability cost satisfying the wirelength constraint

35. Multiple Row Based Optimization • Motivation • A net often spans adjacent rows • Moving cells in different rows simultaneously may reduce wirelength • Some previously “infeasible” manufacturability-driven placement may become “feasible”. More options. • Feasible: satisfy wirelength constraint • Improved manufacturability cost

36. Experiments • Experiment Setup • ISCAS’ 89 (>10K cells in a circuit) and ISPD’ 04 benchmark (>200K cells in a circuit) • 130nm technology • SPLAT for lithography simulation • 1% wire length increase bound • Lookup table size: <1M • Lookup table access time: <0.1ɥs per entry • A Pentium 4 machine with a 3.0GHz CPU 2G memory

37. ISCAS’89: EPE reduction %

38. ISCAS’89: Wirelength Increase %

39. ISCAS’89: Runtime (seconds)

40. Observations • Cell Flipping: • 9% EPE reduction • 0.17% additional wire • Fastest • Single Row Optimization: • 14.6% EPE reduction • 0.35% additional wire • 2x slower compared to Cell Flipping • Multiple Row Optimization • 22% EPE reduction • 0.57% additional wire • 4x slower compared to Cell Flipping

41. ISPD’04: EPE Reduction % 41

42. ISPD’04: Wirelength Increase % Percentage 42

43. ISPD’04: CPU (s) 43

44. Observations Cell Flipping: 11% EPE reduction 0.16% additional wire Very fast Single Row Optimization: 18% EPE reduction 0.29% additional wire 50% slower Multiple Row Optimization: 25% EPE reduction 0.41% additional wire 2x slower 44

45. Conclusion • Propose three algorithms for pattern sensitive placement for manufacturability: • Cell Flipping only • Single Row Optimization • Multiple Row Optimization • >20% edge placement error reduction. • <1% wire length overhead. • Runtime acceptable for large placement benchmark.

46. Thanks