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New Verilog-A capability available in Agilent simulators

New Verilog-A capability available in Agilent simulators. Verilog-A Source. automated compilation. agilent-vacomp. Compiled Model Library (CML). RTE. hpeesofsim. CML Cache. Based on Verilog-A compiler technology of Tiburon Design Automation.

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New Verilog-A capability available in Agilent simulators

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  1. New Verilog-A capability available in Agilent simulators Verilog-ASource automated compilation agilent-vacomp Compiled ModelLibrary (CML) RTE hpeesofsim CMLCache Based on Verilog-A compiler technology of Tiburon Design Automation. Benefits to Compact Model Developers, Foundries and End-users • Simulation speed comparable to C-coded models • Provides the flexibility (e.g. development time, model revisions), ease-of-use (e.g. automatic derivatives, readability) and portability (e.g. EDA vendor independence, model adoption) of the Verilog-A language • Compilation is 'on-the-fly' and fully transparent to the user • IP protection when distributing only the pre-compiled version of the model • All Agilent simulator modes supported (DC, AC, Spar, Transient, Transient Convolution, Harmonic Balance, Circuit Envelope) • Fully supported by Agilent within IC-CAP, ADS and RFDE (ADS simulators in the Cadence Design Environment). • Hicum-L0 (and many other models) provided as examples in Verilog-A source Verilog-A Hicum-L0 example in ADS DC and S-Par simulation results with default parameter values Netlist fragment (instance and model lines) my_hicum_va_model: my_hicum_va_instance _net249 _net250 0 0 _net251 Noise=1 is=8.7e-18 model my_hicum_va_model hicum_l0_va NPN=1 PNP=0 is=8.4e-18 mcf=1.045 mcr=1.05 vef=80 iqf=0.055\ iqr=1e+10 iqfh=1e+10 tfh=1e-08 ibes=3e-20 mbe=1.01 ires=6e-15 mre=2.9 ibcs=7.4e-18 mbc=1.13\ cje0=1.63e-14 vde=0.895 ze=0.525 aje=1.5 t0=1.45e-12 dt0h=7.5e-13 tbvl=9.5e-13 tef0=5e-14\ gte=6 thcs=2.5e-11 ahc=0.1 tr=1e-10 rci0=30 vlim=0.36 vpt=4 vces=0.18 cjci0=1.017e-14 vdci=0.694\ zci=0.393 vptci=4.22 cjcx0=1.67e-15 vdcx=0.588 zcx=0.328 vptcx=1.4 fbc=0 rbi0=6 vr0e=7.4 vr0c=26\ fgeo=0.656 rbx=25 rcx=11 re=1.85 iscs=7.28e-16 msc=1.035 cjs0=8.79e-15 vds=0.348 zs=0.306 vpts=4.44\ cbcpar=3.25e-15 cbepar=1.327e-14 eavl=26.3 kavl=57 kf=0 af=2 vgb=1.17 alb=0 alt0=0 kt0=0 zetaci=0\ alvs=0 alces=0 zetarbi=0 zetarbx=0 zetarcx=0 zetare=0 alkav=0 aleav=0 tnom=20 dt=0 rth=100 cth=0.1e-12 Fragment of Hicum-L0 Verilog-A code Verilog-A code for HICUM Level0 ===================================== This release is based on code developed and written by: 23.11.2002; S.Lehmann & M.Schroter, CEDIC (simplified version of the BJT model HICUM Level2) Code is described in the HICUM/Level0 documentation at www.iee.et.tu-dresden.de/iee/eb/comp_mod.html ===================================== `include "disciplines.vams" `include "constants.vams" `include "compact.vams" module hicum_l0_va(c,b,e,s,tnode); // // Node definitions // inout c,b,e,s,tnode; electrical c,b,e,s; // internal nodes electrical ci,bi,ei; electrical tnode; // default parameter set for level0 parameter real is = 8.4e-18; parameter real mcf = 1.045; parameter real mcr = 1.05; http://eesof.tm.agilent.com/assist/search.cgi?config=eesof&words=verilog-a

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