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ELI Research and Engineering, Inc.

ELI Research and Engineering, Inc. Presents . Do not copy or reproduce without permission of ELI R&E Inc. Certifiable IS Performance. using TOTAL I S T otal O bject-- T otal A ssembly L ine I nformation S ervices.

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ELI Research and Engineering, Inc.

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  1. ELI Research and Engineering, Inc. Presents Do not copy or reproduce without permission of ELI R&E Inc.

  2. CertifiableISPerformance using TOTALI S Total Object--Total Assembly Line Information Services Do not copy or reproduce without permission of ELI R&E Inc.

  3. A Fundamental, not incremental change in computer based Information Technology Architectures Do not copy or reproduce without permission of ELI R&E Inc.

  4. We examine TOTAL IS an architecture which is totally new to Information Processing, but which has been used bymanufacturing since the beginning of the industrialrevolution, to produce o Certifiable quality products at o High rates and low cost. Which can be and often is totally mechanized

  5. With A new Data Processor Architecture Fully Automated Using ALL Hardware control ALL Hardware processes (“programs”)Mechanized processes NOSoftware Do not copy or reproduce without permission of ELI R&E Inc.

  6. Manufacturing Process materials Vendor parts PROCESS PROCESS Vendor parts PROCESS PROCESS Parts Parts PROCESS PROCESS ASSEMBLE Process operate concurrently, Output at stepping rate of assembly line Product

  7. TOTAL Because ALTOPSUsesEngineering disciplines of: Specification,Testing to Specs. Permits Electronic Processing and Assembly lines of 100,000 or more Processing Modules simply connected. (in different locations if desired) - - - oRunning at nanosecond rates, oConcurrently on any number and mix of jobs. o Is Essentially Impenerable Do not copy or reproduce without permission of ELI R&E Inc.

  8. Producing CertifiablyCorrectResults at rates of 100,000 to 1,000,000 per second. Do not copy or reproduce without permission of ELI R&E Inc.

  9. Do not copy or reproduce without permission of ELI R&E Inc.

  10. Do not copy or reproduce without permission of ELI R&E Inc.

  11. PROCESSOR RESOURCE MANAGER The Processor Resource Manager Reads the Job Flow Chart: o Assigns physical Process Nodes to Flow Chart Nodes -Interconnects Processors o Sends Information Manager: -Data class ID’s -Date-time instances o Sends Information Manager: -Port ID’s of Physical I/O Ports o Monitors operations: -Replaces failed units Do not copy or reproduce without permission of ELI R&E Inc.

  12. Information Manager The Information Manager: o Never erases or writes over. Old files are archived o Has separate, independent hardware for: -System Records -System Processes -System Resources -User Data/Information o Reads Job data requirements: - Queues up data - Puts data on Bus to Process Ports as needed Do not copy or reproduce without permission of ELI R&E Inc.

  13. Not to scale 24” Populated columns Plane has 440 chips 748 Function units Performance potential ~1 teraOP Board has 110 Chips 30” 24” System ALTOPS O-T-S Prototype 24” Processor Assembly Line Short Stack, 18 Planes Performance Pot. 18 teraOps Do not copy or reproduce without permission of ELI R&E Inc.

  14. TOTAL ALTOPS (“Off-The-Shelf”) Stack 3 Stack 4 Disks Design Study Stack 1 Stack 2 3,600 giga- byte 5’ 6’ 6’ Machine has107,712 Function Units. Sustained performance potential 140 teraOps/sec. Final result rate for 100,000 instruction commercial job, ~90,000/second Do not copy or reproduce without permission of ELI R&E Inc.

  15. TOTAL Some Performance Estimates of O-T-S ALTOPS(10 teraOp) oMatrix operation, conventional method, (assume 10,000 of chips are pipelined multipliers): For a 10,000x10,000x1000 model: Single plane, 10 to 20 ms. Total model, 10 to 20 sec. Do not copy or reproduce without permission of ELI R&E Inc.

  16. TOTAL Second Generation, (Wafer Scale integration) ALTOPS(3.5 PetaOps) oMatrix multiplication, conventional method, (assume 20,000 of chips are pipelined multipliers): For a 10,000x10,000x1000 model: Single plane, 1 to 2 ms. Total model, 1 to 2 sec. o Note that due to the simple interconnections of the ALTOPS architecture, “Wafer Scale” integration is feasible. Do not copy or reproduce without permission of ELI R&E Inc.

  17. Do not copy or reproduce without permission of ELI R&E inc.

  18. BENEFITS OF TOTAL Efficiency for Business o Automated accounts and audits of all I.S. activity. o Complete model of business Information System in I. S. Specifications enables: o Rapid, accurate evaluation of system changes. o Rapid, accurate modeling of complex data and large models. Do not copy or reproduce without permission of ELI R&E Inc.

  19. BENEFITS OF TOTAL Highest Protection o Maximum Securityand Privacy of Data, No “Virus”, “Bombs”, “Denial of Service” oSystem User cannot invade or discover Intellectual Property of job being used. oJob design owner cannot invade data of User. oSystem Owner cannot invade or discover Intellectual Property of job design or data. Do not copy or reproduce without permission of ELI R&E Inc.

  20. BENEFITS OF TOTAL Efficiency for Business o I. S. responsiveness. New applications running in hours or a few weeks. (Now.average time to develop new applications about 60 months. (Ref.1)) o Results rates 100-1000 times faster on most jobs. o Assured continuous operation, even during major system updates. o More efficient, responsive control of business processes Do not copy or reproduce without permission of ELI R&E Inc.

  21. BENEFITS OF TOTAL Reduces I. S. Cost oReplaces Programming staff with a few experts in the business or industry. Typical saving of 80% of I. S. design cost. (Ref. 1,4) o Saving on average new application, (coded locally) about $10,000,000 (Ref. 1) o Lower cost for system, cooling, less space. Do not copy or reproduce without permission of ELI R&E Inc.

  22. BACKGROUND HOW IT CAME TO BE Note: Many of the following are copies of working documents NOT polished presentation

  23. TODAY’S SOFTWARE IS UNPROVEABLE (Reference 3.) In the early 1970’s Edwards, (IBM Research, Kendall and Lamb (IBM Corp. I.S.) were trying to find a way to make software predictable and reliable.

  24. Hardware can be made: to meet specifications of Performance, Reliability, Accuracy, With reusable, tested components. Hardware can be produced on high speed assembly lines using large # of process stations some geographically separated. Why can’t software?

  25. SAGE (Semi-Automatic Ground Environment) Computer for first computerized air defense system. The IBM contract included specs. for Performance, Reliability, Accuracy, With firm delivery date and penalties The IBM contract was signed 1952

  26. In 1952 there were no: o Computer grade components o On-Line Real Time computer systems o Multiprocessors o Multiprogrammed systems o Systems driven by unskilled operators using graphic displays. Working prototype was delivered 12/54

  27. Factoring Information

  28. Background • Early “Tabulating machines” used by Banks and Industry proved that: • Any class of problem can be solved on a • few different types of machines, • simply connected. • Any number of machines could work together on any problem. • These were electro-mechanical machines • Running typically at 150 functions/minute.

  29. Background • In the early days of electronic computers: • The technology was so expensive only one processor could be afforded. • All jobs were necessarily run on this single processor. • A single computer time-shared system/job control and the problem calculation.

  30. Background o “Compilers”, “Job monitors”, then “Operating Systems” were invented. o “WINDOWS” and other current operating systems are direct derivatives. All time share a single processor o Today’s microprocessor architectures are direct descendants of the early machines.

  31. Background o Typical general purpose processors still use one very fast central processing unit (smaller than your finger nail). o Virus and other invasions of the System are made possible by time-sharing System Control and Applications on a single processor.

  32. Background o Operating Systems and most programs are so complex that verification is not practicable (Ref. 3) Basic code of Windows comprises over 10,000,000 lines of code. o A new 10,000 line program averages about 750 “high severity” defects. when delivered. (Ref. 1) o A C++ programmer spends 80% of effort removing “bugs”

  33. Average # Defects Delivered 80,000 5,000 New Applications 250 Debug, Enhance Ave. Max. Ave. Max. 10,000 100,000 1,000,000 10,000,000 Program Size (lines of code) (after T. Capers Jones 2000)

  34. Average HIGH-SEVERITY Defects Delivered ~ 12,000 New Applications ~ 750 ~ 40 Debug, Enhance Ave. Max. Ave. Max. 10,000 100,000 1,000,000 10,000,000 Program Size (lines of code) (after T. Capers Jones 2000)

  35. Background o “Cache misses” when the CPU must access disks for information greatly reduce the performance of conventional systems. o A cache miss rate of 0.1% reduces the effective performance of a 1 gigaHertz processor to slightly over 0.2 megaHertz. o The TOTAL architecture virtually eliminates cache misses giving efficient performance.

  36. Background o A single processor computing system spends between 70% and 80% of its time in the operating system. The ALTOPS processor in aTOTAL system mechanizes the operating system functions in separate, dedicated hardware running concurrently. Thus time is not lost to the operating system functions.

  37. TOTAL as in hardware manufacturing requires all system Components: oProcessor andSystem control o Materials (data), assemblies (information) o Products (reports, screens, messages) to have Specifications and Accounts that can Be Verified to conform to Specification, including: Function, Reliability and Accuracy . Do not copy or reproduce without permission of ELI R&E Inc.

  38. TOTAL Enabling: (As in hardware manufacture) oReusable, interchangeable data, applications and application components. oAny number of processor nodes of any size or location to cooperate in producing any information product or class of information product. oAssembly Lineproduction, giving a result rate dependent only on the stepping rate of the line, not length. oResults 100,000’s to millions per second. Do not copy or reproduce without permission of ELI R&E Inc.

  39. TOTAL Enabling: (As in hardware manufacture) o Hardware based automation of the system operation, o Hardware process nodes with function adjusted by parameters if desired, oUser applications composed of linked sets of standard, tested hardware modules. No “software” oSystem Security No “virus”, penetrations, “denial of service” Do not copy or reproduce without permission of ELI R&E Inc.

  40. TOTAL Emabling: (As in hardware manufacture) oPrefetching of data Virtually eliminating disk delay. oSelf repair in microseconds. (Tool failure on a factory floor is immediately detected, replaced and the process resumes.) oHardware automated Accounting and Audit of all System Contents, Use, Actions and Configuration. Do not copy or reproduce without permission of ELI R&E Inc.

  41. TOTAL All User interaction is via interactive screens. Users’ View o Information request: User selects from menu: Class Identification and Instance (viz., date time group). oResponse in milliseconds o Run a Job: User selects Job I.D. from menu, fills in instances of data inputs, enters parameters if needed. oResponse in milliseconds Do not copy or reproduce without permission of ELI R&E Inc.

  42. TOTAL CIO View o Authorize new user: Fill in standard screen, Assigns security authorization for department/information class, job class, . . . o Authorize entry of new Application: Verifies job design against spec., adds I.D., Assigns security authorizations. o Authorize entry of new data item: Verifies correct specification, class I.D., Assigns security authorizations. Do not copy or reproduce without permission of ELI R&E Inc.

  43. TOTAL CIO View oRequest and review System Accounts and Audit records. o Modify System/System Function: Order new Function Units from Vendor, or Contact Vendor representative to enter new function code into System Unit ROMs oAuthorizeentry of new Security Check Sum oEstablish and maintain the Classification Structure for the Data, Information, and Applications networks. oSpecify Enterprise Information System structure and performance requirements. Do not copy or reproduce without permission of ELI R&E Inc.

  44. TOTAL Application Designer View oCreate Specification of Application Output oCreate Specification of Data/Information Element inputs, with reliability and accuracy requirement statements. oSpecify algorithm or process to implement application, in normal business terms. oGraphically select and connect Function Modules (note) and existing Total Object Tools “TOTS”(existing Application Components) to construct the application process. Do not copy or reproduce without permission of ELI R&E Inc.

  45. TOTAL Application Designer View oRun the Application prototype on a separate Test Facility to confirm result is to Specification. oObtain authorization from C.I.O. to enter the application into the System.

  46. ALTOPS Second Generation, (Wafer Scale integration) ALTOPS (3.5 PetaOps) o Davis (Ref. 2) Referring to CERN experience and subsequent publications points out that conventional Massively Parallel machines tend to operate at about 10% rated peak rate due to fitting the algorithm to the Single Instruction stream, Multiple Device (SIMD) architecture. Massively Concurrent Machines (ALTOPS) overcome this problem and operate at high efficiency on any class of problem. Do not copy or reproduce without permission of ELI R&E Inc.

  47. (Note) Hardware Function Modules include: o Standard arithmetic and logic functions capable of assembly into any algorithm. o Applications or Application components specific to various classes of business or enterprise. o Standard accounting and audit functions. Do not copy or reproduce without permission of ELI R&E Inc.

  48. References include but are not limited to 1. “Software Assessments, Benchmarks and Best Practices” Jones, Capers, Addison Wesley, 2000 2. “Highly Efficient, High Performance Architectures”, Davis, Dr. Edward, Chair, Computer Science, N.C. State, Proposal to National Science Foundation, 1996

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