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1.2 EMU Electronics. L.S. Durkin CMS Review CERN, September 2003. Outline. Overview of EMU Electronics System Status of EMU Electronics 25 ns Beam Test Results Future Plans Summary. cathode strips. 3 - 16 mm. avalanche. wires. Cathode plane. wires. cathode plane. cathode
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1.2 EMU Electronics L.S. Durkin CMS Review CERN, September 2003
Outline • Overview of EMU Electronics System • Status of EMU Electronics • 25 ns Beam Test Results • Future Plans • Summary
. . . . . . . . . . . . . . cathode strips 3 - 16 mm avalanche wires Cathode plane wires cathode plane cathode strips avalanche 3.1 mm muon 9.5 mm Cathode Strip Chambers • 6-layer chambers • Radial, trapezoidal cathode strips • Azimuthal anode wires • Induced charges on strips - precise f coordinate • Closely spaced wires - fast timing • Wires ganged in groups of 5 -16 for r coordinate
Functions of Electronics • Acquire precise muon data for off-line analysis • Cathode strips: precise f-coordinate (bending direction) determination in each layer by interpolation of induced strip charges. • Anode wire groups: precise timing for bunch crossing tagging and radial position determination. • Generate primitives for Level-1 Trigger • Identify Local Charged Track (LCT) segments using cathode and anode signals
Front-end Requirements • Cathode Electronics • (total signal)/(per channel noise) : 100/1 • peaking time of shaped pulse: 100 ns • digitization precision: 12 bits • dynamic range: 15 MIPs • non-linearity: < 1% • Anode Electronics • peaking time shaped pulse: 30 ns • time slew of discriminated pulses: 2 ns
Anode LCT • Form anode track segment. • Tag bunch crossing of track segment with > 92 % efficiency per chamber Trigger requirements • Cathode LCT • Identify cathode track segment. Pt trigger based on angle of LCT • For Pt threshold of 20-40 GeV requires Dp/p < 30% (in order to limit single muon trigger rate in Level-1 to a few KHz) • Track hits must be located to within ½ strip width in each chamber layer
The LHC Environment • Charge Particle Rates in EMU • Punch through, hadrons, muons: Rates range from 10 Hz cm-2 (outer ME 3,4) to 300 Hz cm-2 (inner ME1) • Random hits induced by neutrons and photons: Rates can be as high as 500 Hz cm-2 (inner ME1) (Calculations based on TDR shielding) • Radiation Levels at the CSC’s Integrated over 10 LHC years (5x107 s at 1034 cm-2s-1) • Neutron Fluence (>100 keV): (0.02 - 6) x 1011 cm-2 • Total Ionizing Dose: (0.007 - 1.8) kRad • Levels at the iron disk peripheral about 10 times lower • (Calculations by M. Huhtinen)
Trig Motherboard Clock Control Board DDU Board DAQ Motherboard C C B D M B T M B D M B T M B D M B T M B D M B T M B D M B T M B M P C T M B D M B T M B D M B T M B D M B T M B D M B Slow Control C O N T R O L L E R Muon Sector Receiver Lev-1 Trigger Readout Data Trigger-Timing-Control Peripheral Crate on iron disk FED Crate in USC55 1 of 5 1 of 5 Cathode Front-end Board CFEB CFEB CFEB CFEB CFEB 1 of 2 LV Distribution Board 1 of 24 ALCT LVDB Anode LCT Board Anode Front-end Board CSC System Layout
on-chamber Peripheral Crates FED Crates Total Board Count
2001-02 Final prototype boards Performance tests Radiation tests Finalize design Nov- 03 CMS Electronics System Review 2004-05 Production C C B D M B T M B D M B T M B D M B T M B D M B T M B D M B T M B M P C T M B D M B T M B D M B T M B D M B T M B D M B C O N T R O L L E R CFEB CFEB CFEB CFEB CFEB 1999-2000 Final CFEB & AFEB prototypes tested (Performance, radiation) 2000 ALCT prototype tested Sep-2000 CMS Electronics System Review 2001 Start CFEB, AFEB production 2002 Start ALCT, LVDB production 2003 Finish production 1 of 2 1 of 24 ALCT LVDB CSC EMU Electronics Schedule
Anode Front-end Board CFEB CFEB CFEB CFEB CFEB Cathode Front-end Board ALCT LVDB CSC Low Voltage Distribution Board Anode LCT Board On-Chamber Electronics
Status: On-Chamber Boards • Beam tests (GIF at CERN, 9/1999) of on-chamber boards showed that they met design specifications. • Tests with 60 Mev protons and 1 MeV neutrons (UCD, OSU 5/2000) verified that the boards are tolerant to radiation at 3 times the calculated levels. • Tests in magnetic fields (8/2000 at OSU, UCLA and FNAL) showed that the boards operate beyond 3.5 T. • Spark protection circuits on CFEB and AFEB tested extensively with induced chamber sparks. • Approved for production (CFEB, AFEB in 9/00; ALCT, LVDB in 11/01). • Production of on-chamber boards is on schedule and within the budget.
ALCT- 672 ALCT- 384 ALCT- 288 ALCT Production
LVDB Production • All LVMB plus cables produced. • LVDB Production caught up with schedule:
DAQ Motherboard (DMB) • Initiates FE digitization and readout • Receives and sends FE data to DDU • Provides Slow Control interface to • FE boards (VME-JTAG) C C B D M B T M B D M B T M B D M B T M B D M B T M B D M B T M B M P C T M B D M B T M B D M B T M B D M B T M B D M B C O N T R O L L E R • TRIG Motherboard (TMB) • Generates Cathode LCT trigger • Receives ALCT data from FE • Matches ALCT and CLCT • Sends trigger primitive to Lev-1 • Crate Controller • Interface to DCS • Provide Slow Control services • Download FPGA, thresholds, • calibration constants; LV • monitoring, debug electronics. • Clock Control Board (CCB) • Interfaces to the TTC system • Distributes LHC clock, resets, • L1- Accept EMU Peripheral Crates in UXC55
EMU Peripheral Crates • Total of 60 crates in EMU • 2 x (12 crates on YE1), serving ME1 station • 2 x (12 crates on YE2), serving ME2,3 stations • 2 x ( 6 crates on YE3), serving ME4 station • Crate type • 9U VME cage with custom LV power and cooling • Each crate has a custom backplane in addition to the standard VME backplane • Power consumption: 175 W per crate • Requires +3.3V, +5V, -12V • Radiation background (M. Huhtinen) • Per 10 LHC yrs: Neutron fluence 4x1010 cm-2, Ionization dose 1.3 Gy
600 600 Rack for Peripheral Crates • Each 600 x 600 rack houses two crates • LV Power – custom regulator boards feed off AC-DC converters. • Cooling – plan to use tangential fan with magnetically shielded motor. • Special strain relief for the input cables designed.
Peripheral Crate Electronics Status • “Final” prototypes of DMB, TMB, CCB, Custom Backplane produced and bench tested. • FPGA firmware for all boards completed. • Dynatem (Controller) software written and tested. • A new, simpler controller being prototyped. • TTC software installed (CCB) and working. • Rad-hard solution of CCB using discrete logic under consideration. • All skew-clear cable (including ME1/1) produced and delivered to CERN. • Prototype Peripheral Crate electronics have been tested with 2 fully instrumented CSC in 25ns beam at X5A. Preliminary test results look good.
1.2 ms 23 ms SPS orbit period 2003 Time-Structured Test Beam 48 bunches 25 ns bunch spacing bunch width 3-5 ns Structure repeats during 2.6 s spill length
2003 Time-structured Beam Test Setup TTC crate Trigger primitives DAQ Data PC Peripheral Crate 2 DMB, 2 TMB 1 CCB, 1 MPC FED crate 1 DDU Track finder Crate TRIDAS beam S1 S3 S2 CSC 2 CSC 1
25ns BXN ID Using ALCT and TTC System • Anode timing resolution measured in 1999 beam test • ALCT can be used as timing mark for each CSC hit. • LHC clock from the TTC system will be used as a “TDC” to locate ALCT’s with respect to BC0 (start of LHC orbit). • A primary goal of the time-structured beam test is to validate the peripheral crate electronics’ capability to unambiguously tag CSC hits using the TTC system and anode timing. ALCT time using TDC s=3.9 ns Time (ns)
L!A (Beam Scintillation Counters) 48 bunches BX Number ALCT (Anode trigger Primitive) 48 bunches BX Number BXN for L1A and ALCT (2003 beam test)
L1ABXN- ALCTBXN (2003 Beam Test) (L1A is scintillation counter in beam) • In a single CSC module, 98.7 % of events in one bunch count. With 2 or more CSC’s, probability is higher than 99.9 %. • EMU system’s ability to tag BXN for each CSC hit using the TTC system has been validated. CSC #2 CSC #1
1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -100 0 100 200 300 400 500 600 Time (ns) CFEB Pulse Shape Cathode pulses were fitted by constraining peak to 133 ns Start time (Ts) and pulse height (P.H.) were extracted from fits. Plot shows digitized samples overlaid for all 500 pulses with Ts aligned and PH normalized to 1.
140 120 100 80 60 40 20 0 bin width = 0.2 (5 ns) • 750 760 770 780 790 800 • Bunch Crossing Number Timing from Cathode Strips Cathode pulse timing (6 layer average) relative to L1A (beam scintillators)
600 500 400 300 200 100 0 Single layer resolution ME2,3/2 chamber Spatial resolution (mm) -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Distance from edge of strip (unit: strip width) Spatial Resolution from Cathode Strips • Resolution is best for hit near the edge of strip, worst at the center. • In a CSC, the 6 layers are staggered alternately by ½ strip width. • The combined resolution is ~ 100 mm per chamber
Chamber #1 CLCT 2,000 1,500 CLCT Rate (KHz) 1,000 data consistent with dead-time = 225 ns 500 0 0 500 1,000 1,500 2,000 2,500 3,000 Beam Intensity (KHz) Expected LCT rate at LHC < 25 KHz (ME1/1) Trigger Rate Tests
25 ns Beam Test Results/Status • ALCT BX number relative to L1A - 98.7 % in one bunch count. EMU system’s ability to tag BXN for each CSC hit using the TTC system has been validated. • Efficiencies ~ 99% for both ALCT and CLCT • Lowered AFEB, Comparator thresholds (low CSC gas gain) • offline cuts to eliminate junk events • Cathode strip timing and spatial resolution satisfactory. • A lot of ALCT, CLCT data vs CSC angles (q, Y) was taken. • DAQ rate tests carried out with high intensity pion beam. • 100 KHz L1A (scintillators), 100 KHz LCT, 1 Kz matched L1A-LCT with 16 SCA sample readout. No Problems. • When L1A-LCT matching increased to 10 KHz, event got over written, DMB buffer not empty. • Repeat above with 8 sample readout. No problems. • Preliminary CLCT, ALCT trigger rate tests look OK.
Electronics Control • Fast Control • Reload FPGA’s to recover from SEU • Reset buffers to restore synchronization • Resets will come from TTCrx via the Clock Control Board • Slow Control (part of DCS) • Download FPGA firmware • Down load thresholds • Download calibration constants • Debug electronics • Monitor LV voltages, currents • Monitor board temperatures.
Peripheral Crate Controller Dynatem D360 (baseline) • 25 MHz 68EN360 Processor • Communicates with Linux PC (in USC55) via 10 Base FL Ethernet • Operating System: mCLinux • Software for PC-D360-VME communications have been written and tested. • Radiation tolerant • Tested with 63 MeV protons. Observed 35 upsets in a fluence of 0.74x1011 p’s/cm2. Recover from upsets with “system reset”. Requires 47 resets in 10 LHC-years. • Speed • Transfer rate ~ 2.5 Mbits/s continuous. • Speed of loading FPGA firmware to EPROM dominated by required erase/program delays on chip. • Cost ~ $1100 per unit
A New Crate Controller in Development • A simple custom board containing • XILINX Virtex-II Pro with built in Gigabit Ethernet • Optical transceiver (for Gigabit Ethernet) • Advantages • A much simpler crate controller • Communicates with stand-alone PC (in USC55) via ethernet • Gigabit ethernet PCI card commercially available • All programming done on PC. No controller specific software. • Fast: transfer rate ~ 1 Mbits/s • Inexpensive: ~ $600 per unit • Status of development (at Ohio State Univ) • XILINX II Pro now available • Firmware for Gigabit ethernet already exits. • Firmware for a limited VME master to be developed.
Detector Dependent Unit Receive data from Frontend, Format and send data to DCC Detect and report errors D D U D D U D D U D C C D D U D D U C R A T E C O N T R O L L E R D D U D D U D C C D D U D D U Data Concentration Card Receive data from DDU’s Merge and send data to DAQ via S-Link Crate Controller Interface to DCS Provide Slow Control services 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 EMU FED Crate (in USC55) • EMU will have 4 FED crates in USC55. • Each FED crate houses 9 DDU’s and 2 DCC’s • Latest rack layout for EMU in USC confirmed. (http://cmsdoc.cern.ch/~wsmith/USC55_racks_v40a.html)
DDU Prototype • First 9U DDU board produced and tested. (2002) • Full error checking implemented • Interface to VME • PC readout via Gigabit Ethernet (90 MB/s data transfer) • DMB calibration pulses, regular and random timing • S-Link64 tested • Need to integrate w/ FMM and TTS
Looking Ahead • Tests of EMU Electronics system – for validation of peripheral crate electronics prior to ESR and production. • Use multiple chambers and multiple peripheral crates. • Tests with Cosmic rays at UCLA by end of April ‘03 • Test with 25 ns beam at CERN in May ‘03 • Radiation tolerant tests of all peripheral crate boards (60 MeV protons at UCD) by Sep 03. • Tolerance of all components to a level of 3x1011 n’s/cm2 • Finalize scheme to make CCB immune to SEU. • ESR of full EMU electronics system - Nov 03 • Start production for peripheral crate boards by end of 03. • Installation and commissioning of CSC’s on iron disks at SX5 in 2003-04 • Slice test together with TRIDAS planned for 2004-05.
Joint EMU-TRIDAS Slice Test TTC crate Trigger primitives Muon Trigger Crates DAQ Data Standalone DAQ PC FED crate Peripheral crates ME3 DCS ME2 cosmic ray ME1 Slice Test planned for 2004-05 (Key Milestone, L3 Task in M&O)
Summary • On-chamber boards met performance requirements and passed extensive radiation, magnetic field and sparking tests. • Production of on-chamber boards is on schedule and within budget. • Prototype work of all off-chamber boards (in peripheral crates and in FED crates) are in advanced stages. • Integrated EMU electronics system works well and tested successfully in 25 ns time-structured beam at CERN (May23 – June1, 2003). • Production review of Peripheral crate electronics in Nov 2003. Production scheduled to start in 2004. • EMU Electronics is in good shape.