High Level Design & ESL

1. High Level Design & ESL How design cost is driving innovation in system-level designs? Rajesh Gupta University of California, San Diego FMCAD, Portland, Nov. 17, 2008 mesl . ucsd . edu

2. My main point • At various time VLSI design has been driven by • Area, timing, power, reliability, manufacturing variability • Cost of design is likely to be the driver for future innovations in how we architect, design and implement future ICs in each of these areas: • Tools, Methods • Architectures • Programming models and methods

3. Systems Tools Mask data Components Masks The Technology and Its Industry

4. More Silicon to More Boxes… Of the 72 distinct application markets that rely on value added IC designs (ASIC, ASSP, FPGA, SOC) over 50% are less than $500M, 75% are less than $1B The rising fabless, fablite The US has 56% of over 1K design houses… …and accounts for 76% of industry revenues (Wireless 27%, networking 25%, consumer 20%) Cost is increasingly the driver for fabless Only 17% of designs above 500 MHz 67% of ASIC designs are 299 MHz and lower Sizes pretty much evenly distributed from 100K to 5M gates Source: IBS

5. Is there a problem here? Source: Gartner Dataquest “ASIC and FPGA WW Market Forecast, January 2008”

6. More & Moore Pad limited die: 200 pins 52 mm2 • Most things in real-life do not scale anywhere close to this • Battery energy, power sources • Size, Space, Spectrum • Design time. • Dealing with the effects of Moore • “Embedded Systems” 486

7. A Tale of Two Consequence • EDA: Raise abstractions • Raising abstraction has always been part of the solution strategy to lower design costs. • In design modeling, design synthesis, design verification • Architecture: Raise programmability • Holy Grail: ASIC efficiency with CPU programmability. • The tremendous space of architectural innovations between ASIC and FPGA • Let us take a look at the two sides from a familiar perspective

8. FPGA v. ASIC: Cost v. Volume Structured ASIC, SA New Fabric, T ct • A good solution: • xf 0 or better ASIC, ct cf • xa infinity or better FPGA, mtma xf xa Total Cost FPGA ASIC ca cf Volume • Currently we are: cf = 2 ca ; mf = 20 ma • Fixed cost of FPGA design = 2 * ASIC design costs • Per part cost of FPGAs rises 20x cost of ASIC. • Current crossover point at 100K units.

9. ASIC/FPGA Tradeoff SA T ct • A good solution: • xf 0 or better ASIC, ct cf • xa infinity or better FPGA, mtma xf xa Total Cost F A ca cf Volume

10. Better ASIC orBetter FPGA? Improved Area Utilization Reduced Design Cost; Chip implementation, Shuttles, etc. Space of ‘synthetic’ solutions Total Cost F A ca cf Volume

11. F F A A ca ca Total Cost Better area utilization in FPGA, 7x target Better synthesis, EDA, 2x target cf cf Volume F A ca Design for synthesis, 3x cost increase cf

12. Technical Dimensions of the Problem • SE: Silicon Efficiency • Inherently better circuit implementation styles, levels, logic: Asynchronous, GALS • AE: Architectural Efficiency • Inherently improved application-level performance or performance independent of mapping methods • PA: Programmer Accessibility • Use existing programming models/methods to ensure IP availability and integration. • DP: Designer Productivity

13. ITRS, last updated 2006 Designer Productivity is Challenge #1 Verification Predictable Implementation Embedded SW Distributed design, AMS

14. Impact on Designer Productivity

15. Automatic Test Generation Partial Order Reduction Architecture Level Transaction Level Model (TLM) (Non-Synthesizable Subset) Explicit Stateless Search Property Checker Property checker Mostly Manual Automated Theorem Proving Translation Validation Micro-architecture Level (Synthesizable Subset) Refinement or Equivalence Checker High Level Synthesis Relational Approach Refinement/Equivalence checker Register Transfer Level (RTL) Verification Techniques Verification Techniques Raising Verification • Scalable techniques for automatic verification of system designs Golden Reference Model

16. Refinement Or Equivalent Checker Checker Refinement Checking Input Program (Specification) Transformed Program (Implementation) Transformations

17. CSP Specification CSP Implementation Front End Parser A R C C o S Implementation (CFG) Specification (CFG) Simulation Relation Inference Engine Checking Engine Automated Theorem Prover (Simplify) Partial Order Reduction Engine Prototype Implementation - ARCCoS

18. Results from ARCCoS

19. + + < a0 b0 Resource Allocation: i1: sum = 0 j1: sum = 0 j2: k = p j41: t = p + 1 i2: k = p j3: (k < 10) j6: ¬ (k < 10) i3: (k < 10) i6: ¬ (k < 10) j7: return sum j4: k = t j5: sum = sum + t j42: t = t + 1 i7: return sum i4: k = k + 1 (b) Implementation i5: sum = sum + k (a) Specification a1 a2 b1 a3 a5 b2 b3 a6 a4 b4 Example Loop pipelining Copy propagation sum = ∑10i p+1

20. On going work Intermediate Representation Static Analysis SystemC Design Partial Order Information Test Bench Query Engine Explore Engine SystemC Simulator Explicit Stateless Model Checker Satya

21. Closing Thoughts • ASIC design cost is the new driver • Solution space is expanded to include not only tools but also architectures • A time for tremendous creativity