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ITRS 2009 ITWG Spring Meeting March 19-20 Brussels FEP Highlights and Notes

ITRS 2009 ITWG Spring Meeting March 19-20 Brussels FEP Highlights and Notes. FEP ITWG Spring 2009 Participants. FEP: Highlights and Key Challenges. PIDS and FEP working on introducing a new approach to track scaling Introduce RO delay as a new metric to track in addition to CV/I

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ITRS 2009 ITWG Spring Meeting March 19-20 Brussels FEP Highlights and Notes

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  1. ITRS 2009 ITWG Spring MeetingMarch 19-20BrusselsFEP Highlights and Notes

  2. FEP ITWG Spring 2009 Participants

  3. FEP: Highlights and Key Challenges • PIDS and FEP working on introducing a new approach to track scaling • Introduce RO delay as a new metric to track in addition to CV/I • Need to accelerate CV/I determination for 2009 to meet time lines for 2009 roadmap • Lg scaling: need to reflect potentially slower scaling trends • All 32nm reports indicate Lg ~ 30 nm • Working with PIDS team; ORTC resolution needed • Need to update insertion time lines for new device options • HKMG, high mobility channels, MuGFET, FDSOI • For HP, LOP, LSTP • Need to understand implications for a scenario where 3D devices come before high mobility channels • Cannot be possible for industry to use 3D for one generation and switch back to planar! • Dictates that industry would most likely need to investigate 3D high mobility channels • High mobility channels likely to be introduced selectively along with Si devices • Requires process advancements in epi, buffer layers, interfaces • Require analysis and solutions for contamination control, cleaning protocols etc

  4. FEP: Highlights and Key Challenges (cont) • Flash memory scaling challenges: Fill of HAR isolation trench is a key challenge for scalability of FGC • NAND scaling likely to push FGC cell – may need high-k in the stacks; CTF is also an attractive option: requires trap layers/band engineering • NOR scaling – do we need it (business reasons) can we do it (technical reasons) • Potential replacement solutions: MRAM (STT?), PCRAM..? Other..? Do we need to bring them in? • Defect/particle in-line metrology needed at 0.5 CD or better  need ~10 nm capability for 22 nm generation • Critical areas: for new channel epi, scaled contacts, gate stacks.. • Need compositional information + thickness information for various stacks (HKMG, high mob channels etc) • Metrology related to ERD materials and devices (GST/STT stack….) • Impact of 3D interconnects (TSV) on device performance, reliability • Stress from back grinding and polish – impact on device performance + reliability • Will determine integration options and design implications for placement of TSVs • ERM and FEP working on future doping strategies • Monolayer diffusion doping approach may be the most manufacturable method

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